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Sergey Yarkov 2022-05-29 01:05:53 +03:00
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AVRASM ver. 2.2.7 firmware.asm Sun May 29 00:54:54 2022
[builtin](2): Including file 'C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn2313Adef.inc'
[builtin](2): Including file 'C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn2313Adef.inc'
;
;***** Created: 2011-02-09 12:04 ******* Source: ATtiny2313A.xml *********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "tn2313Adef.inc"
;* Title : Register/Bit Definitions for the ATtiny2313A
;* Date : 2011-02-09
;* Version : 2.35
;* Support E-mail : avr@atmel.com
;* Target MCU : ATtiny2313A
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _TN2313ADEF_INC_
#define _TN2313ADEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATtiny2313A
#pragma AVRPART ADMIN PART_NAME ATtiny2313A
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x91
.equ SIGNATURE_002 = 0x0a
#pragma AVRPART CORE CORE_VERSION V2
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ OCR0B = 0x3c
.equ GIMSK = 0x3b
.equ EIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ SPMCSR = 0x37
.equ OCR0A = 0x36
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0B = 0x33
.equ TCNT0 = 0x32
.equ OSCCAL = 0x31
.equ TCCR0A = 0x30
.equ TCCR1A = 0x2f
.equ TCCR1B = 0x2e
.equ TCNT1L = 0x2c
.equ TCNT1H = 0x2d
.equ OCR1AL = 0x2a
.equ OCR1AH = 0x2b
.equ OCR1BL = 0x28
.equ OCR1BH = 0x29
.equ CLKPR = 0x26
.equ ICR1L = 0x24
.equ ICR1H = 0x25
.equ GTCCR = 0x23
.equ TCCR1C = 0x22
.equ WDTCR = 0x21
.equ PCMSK0 = 0x20
.equ EEAR = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTA = 0x1b
.equ DDRA = 0x1a
.equ PINA = 0x19
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ GPIOR2 = 0x15
.equ GPIOR1 = 0x14
.equ GPIOR0 = 0x13
.equ PORTD = 0x12
.equ DDRD = 0x11
.equ PIND = 0x10
.equ USIDR = 0x0f
.equ USISR = 0x0e
.equ USICR = 0x0d
.equ UDR = 0x0c
.equ UCSRA = 0x0b
.equ UCSRB = 0x0a
.equ UBRRL = 0x09
.equ ACSR = 0x08
.equ BODCR = 0x07
.equ PRR = 0x06
.equ PCMSK2 = 0x05
.equ PCMSK1 = 0x04
.equ UCSRC = 0x03
.equ UBRRH = 0x02
.equ DIDR = 0x01
; ***** BIT DEFINITIONS **************************************************
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR - Timer/Counter Interrupt Flag register
.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; OCR0B - Timer/Counter0 Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0A_0 = 0 ;
.equ OCR0A_1 = 1 ;
.equ OCR0A_2 = 2 ;
.equ OCR0A_3 = 3 ;
.equ OCR0A_4 = 4 ;
.equ OCR0A_5 = 5 ;
.equ OCR0A_6 = 6 ;
.equ OCR0A_7 = 7 ;
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Match Output B Mode
.equ COM0B1 = 5 ; Compare Match Output B Mode
.equ COM0A0 = 6 ; Compare Match Output A Mode
.equ COM0A1 = 7 ; Compare Match Output A Mode
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; TCCR0B - Timer/Counter Control Register B
.equ TCCR0 = TCCR0B ; For compatibility
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare B
; ***** TIMER_COUNTER_1 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
.equ TICIE = ICIE1 ; For compatibility
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
; TIFR - Timer/Counter Interrupt Flag register
.equ ICF1 = 3 ; Input Capture Flag 1
.equ OCF1B = 5 ; Output Compare Flag 1B
.equ OCF1A = 6 ; Output Compare Flag 1A
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
.equ PWM10 = WGM10 ; For compatibility
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
.equ PWM11 = WGM11 ; For compatibility
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Clock Select bit 0
.equ CS11 = 1 ; Clock Select 1 bit 1
.equ CS12 = 2 ; Clock Select1 bit 2
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
.equ CTC1 = WGM12 ; For compatibility
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1B = 6 ; Force Output Compare for Channel B
.equ FOC1A = 7 ; Force Output Compare for Channel A
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** USART ************************
; UDR - USART I/O Data Register
.equ UDR0 = 0 ; USART I/O Data Register bit 0
.equ UDR1 = 1 ; USART I/O Data Register bit 1
.equ UDR2 = 2 ; USART I/O Data Register bit 2
.equ UDR3 = 3 ; USART I/O Data Register bit 3
.equ UDR4 = 4 ; USART I/O Data Register bit 4
.equ UDR5 = 5 ; USART I/O Data Register bit 5
.equ UDR6 = 6 ; USART I/O Data Register bit 6
.equ UDR7 = 7 ; USART I/O Data Register bit 7
; UCSRA - USART Control and Status Register A
.equ USR = UCSRA ; For compatibility
.equ MPCM = 0 ; Multi-processor Communication Mode
.equ U2X = 1 ; Double the USART Transmission Speed
.equ UPE = 2 ; USART Parity Error
.equ PE = UPE ; For compatibility
.equ DOR = 3 ; Data overRun
.equ FE = 4 ; Framing Error
.equ UDRE = 5 ; USART Data Register Empty
.equ TXC = 6 ; USART Transmitt Complete
.equ RXC = 7 ; USART Receive Complete
; UCSRB - USART Control and Status Register B
.equ UCR = UCSRB ; For compatibility
.equ TXB8 = 0 ; Transmit Data Bit 8
.equ RXB8 = 1 ; Receive Data Bit 8
.equ UCSZ2 = 2 ; Character Size
.equ CHR9 = UCSZ2 ; For compatibility
.equ TXEN = 3 ; Transmitter Enable
.equ RXEN = 4 ; Receiver Enable
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE = 6 ; TX Complete Interrupt Enable
.equ RXCIE = 7 ; RX Complete Interrupt Enable
; UCSRC - USART Control and Status Register C
.equ UCPOL = 0 ; Clock Polarity
.equ UCSZ0 = 1 ; Character Size Bit 0
.equ UCSZ1 = 2 ; Character Size Bit 1
.equ USBS = 3 ; Stop Bit Select
.equ UPM0 = 4 ; Parity Mode Bit 0
.equ UPM1 = 5 ; Parity Mode Bit 1
.equ UMSEL0 = 6 ; USART Mode Select 0
.equ UMSEL1 = 7 ; USART Mode Select 1
.equ UCPHA = 1 ; USART MSPIM Clock Phase
.equ UDORD = 2 ; USART MSPIM Data Order
.equ UBRR = UBRRL ; For compatibility
; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIC = 2 ;
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ ACBG = 6 ; Analog Comparator Bandgap Select
.equ ACD = 7 ; Analog Comparator Disable
; DIDR - Digital Input Disable Register 1
.equ AIN0D = 0 ; AIN0 Digital Input Disable
.equ AIN1D = 1 ; AIN1 Digital Input Disable
; ***** PORTD ************************
; PORTD - Data Register, Port D
.equ PORTD0 = 0 ;
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ;
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ;
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ;
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ;
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ;
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ;
.equ PD6 = 6 ; For compatibility
; DDRD - Data Direction Register, Port D
.equ DDD0 = 0 ;
.equ DDD1 = 1 ;
.equ DDD2 = 2 ;
.equ DDD3 = 3 ;
.equ DDD4 = 4 ;
.equ DDD5 = 5 ;
.equ DDD6 = 6 ;
; PIND - Input Pins, Port D
.equ PIND0 = 0 ;
.equ PIND1 = 1 ;
.equ PIND2 = 2 ;
.equ PIND3 = 3 ;
.equ PIND4 = 4 ;
.equ PIND5 = 5 ;
.equ PIND6 = 6 ;
; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ EEARL = EEAR ; For compatibility
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEWE = EEPE ; For compatibility
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EEMWE = EEMPE ; For compatibility
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
.equ EEPM0 = 4 ;
.equ EEPM1 = 5 ;
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
; ***** USI **************************
; USIDR - USI Data Register
.equ USIDR0 = 0 ; USI Data Register bit 0
.equ USIDR1 = 1 ; USI Data Register bit 1
.equ USIDR2 = 2 ; USI Data Register bit 2
.equ USIDR3 = 3 ; USI Data Register bit 3
.equ USIDR4 = 4 ; USI Data Register bit 4
.equ USIDR5 = 5 ; USI Data Register bit 5
.equ USIDR6 = 6 ; USI Data Register bit 6
.equ USIDR7 = 7 ; USI Data Register bit 7
; USISR - USI Status Register
.equ USICNT0 = 0 ; USI Counter Value Bit 0
.equ USICNT1 = 1 ; USI Counter Value Bit 1
.equ USICNT2 = 2 ; USI Counter Value Bit 2
.equ USICNT3 = 3 ; USI Counter Value Bit 3
.equ USIDC = 4 ; Data Output Collision
.equ USIPF = 5 ; Stop Condition Flag
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
.equ USISIF = 7 ; Start Condition Interrupt Flag
; USICR - USI Control Register
.equ USITC = 0 ; Toggle Clock Port Pin
.equ USICLK = 1 ; Clock Strobe
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
.equ USISIE = 7 ; Start Condition Interrupt Enable
; ***** EXTERNAL_INTERRUPT ***********
; GIMSK - General Interrupt Mask Register
.equ PCIE1 = 3 ;
.equ PCIE2 = 4 ;
.equ PCIE0 = 5 ;
.equ INT0 = 6 ; External Interrupt Request 0 Enable
.equ INT1 = 7 ; External Interrupt Request 1 Enable
; EIFR - Extended Interrupt Flag Register
.equ GIFR = EIFR ; For compatibility
.equ PCIF0 = 5 ;
.equ PCIF2 = 4 ;
.equ PCIF1 = 3 ;
.equ INTF0 = 6 ; External Interrupt Flag 0
.equ INTF1 = 7 ; External Interrupt Flag 1
; PCMSK2 - Pin Change Interrupt Mask Register 2
.equ PCINT11 = 0 ; Pin Change Interrupt Mask 11
.equ PCINT12 = 1 ; Pin Change Interrupt Mask 12
.equ PCINT13 = 2 ; Pin Change Interrupt Mask 13
.equ PCINT14 = 3 ; Pin Change Interrupt Mask 14
.equ PCINT15 = 4 ; Pin Change Interrupt Mask 15
.equ PCINT16 = 5 ; Pin Change Interrupt Mask 16
.equ PCINT17 = 6 ; Pin Change Interrupt Mask 17
; PCMSK1 - Pin Change Interrupt Mask Register 1
.equ PCINT8 = 0 ; Pin Change Interrupt Mask 8
.equ PCINT9 = 1 ; Pin Change Interrupt Mask 9
.equ PCINT10 = 2 ; Pin Change Interrupt Mask 10
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; SPMCSR - Store Program Memory Control and Status register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ RFLB = 3 ; Read Fuse and Lock Bits
.equ CTPB = 4 ; Clear Temporary Page Buffer
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
.equ SM0 = 4 ; Sleep Mode Select Bit 0
.equ SM = SM0 ; For compatibility
.equ SE = 5 ; Sleep Enable
.equ SM1 = 6 ; Sleep Mode Select Bit 1
.equ PUD = 7 ; Pull-up Disable
; CLKPR - Clock Prescale Register
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
; MCUSR - MCU Status register
.equ PORF = 0 ; Power-On Reset Flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
; OSCCAL - Oscillator Calibration Register
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
; GTCCR - General Timer Counter Control Register
.equ SFIOR = GTCCR ; For compatibility
.equ PSR10 = 0 ;
; PCMSK - Pin-Change Mask register
.equ PCINT0 = 0 ; Pin-Change Interrupt 0
.equ PCINT1 = 1 ; Pin-Change Interrupt 1
.equ PCINT2 = 2 ; Pin-Change Interrupt 2
.equ PCINT3 = 3 ; Pin-Change Interrupt 3
.equ PCINT4 = 4 ; Pin-Change Interrupt 4
.equ PCINT5 = 5 ; Pin-Change Interrupt 5
.equ PCINT6 = 6 ; Pin-Change Interrupt 6
.equ PCINT7 = 7 ; Pin-Change Interrupt 7
; GPIOR2 - General Purpose I/O Register 2
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
; GPIOR1 - General Purpose I/O Register 1
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
; GPIOR0 - General Purpose I/O Register 0
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
; PRR - Power reduction register
.equ PRUSART = 0 ;
.equ PRUSI = 1 ;
.equ PRTIM0 = 2 ;
.equ PRTIM1 = 3 ;
; BODCR - BOD control register
.equ BPDSE = 0 ;
.equ BPDS = 1 ;
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ CKOUT = 6 ; Clock output
.equ CKDIV8 = 7 ; Divide clock by 8
; HIGH fuse bits
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ WDTON = 4 ; Watchdog Timer Always On
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ DWEN = 6 ; debugWIRE Enable
.equ RSTDISBL = 7 ; External reset disable
; EXTENDED fuse bits
.equ SELFPRGEN = 0 ; Self Programming Enable
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x03ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 128
.equ RAMEND = 0x00df
.equ XRAMEND = 0x0000
.equ E2END = 0x007f
.equ EEPROMEND = 0x007f
.equ EEADRBITS = 7
#pragma AVRPART MEMORY PROG_FLASH 2048
#pragma AVRPART MEMORY EEPROM 128
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x0
.equ NRWW_STOP_ADDR = 0x3ff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x0
.equ PAGESIZE = 16
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt Request 0
.equ INT1addr = 0x0002 ; External Interrupt Request 1
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
.equ OC1addr = 0x0004 ; For compatibility
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
.equ URXCaddr = 0x0007 ; USART, Rx Complete
.equ URXC0addr = 0x0007 ; For compatibility
.equ UDREaddr = 0x0008 ; USART Data Register Empty
.equ UDRE0addr = 0x0008 ; For compatibility
.equ UTXCaddr = 0x0009 ; USART, Tx Complete
.equ UTXC0addr = 0x0009 ; For compatibility
.equ ACIaddr = 0x000a ; Analog Comparator
.equ PCIBaddr = 0x000b ; Pin Change Interrupt Request B
.equ PCIaddr = 0x000b ; For compatibility
.equ OC1Baddr = 0x000c ;
.equ OC0Aaddr = 0x000d ;
.equ OC0Baddr = 0x000e ;
.equ USI_STARTaddr = 0x000f ; USI Start Condition
.equ USI_OVFaddr = 0x0010 ; USI Overflow
.equ ERDYaddr = 0x0011 ;
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
.equ PCIAaddr = 0x0013 ; Pin Change Interrupt Request A
.equ PCIDaddr = 0x0014 ; Pin Change Interrupt Request D
.equ INT_VECTORS_SIZE = 21 ; size in words
#endif /* _TN2313ADEF_INC_ */
; ***** END OF FILE ******************************************************
; Project name: sleep-mode-example
; Description: Example of using sleep mode in power-down mode on avr microcontroller
; Source code: https://github.com/sergeyyarkov/attiny2313a_sleep-mode-example
; Device: ATtiny2313A
; Package: 20-pin-PDIP_SOIC
; Assembler: AVR macro assembler 2.2.7
; Clock frequency: 8MHz with CKDIV8
; Fuses: lfuse: 0x64, hfuse: 0x9F, efuse: 0xFF, lock:0xFF
;
; Written by Sergey Yarkov 29.05.2022
.list
.def temp_r = r16
.def wdt_counter = r10
.dseg ; Data segment
.org SRAM_START
.cseg ; Code segment
.org 0x00
000000 c01a rjmp RESET_vect ; External Pin, Power-on Reset, Brown-out Reset, and Watchdog Reset
000001 9518 reti ; External Interrupt Request 0
000002 9518 reti ; External Interrupt Request 1
000003 9518 reti ; Timer/Counter1 Capture Event
000004 9518 reti ; Timer/Counter1 Compare Match A
000005 9518 reti ; Timer/Counter1 Overflow
000006 9518 reti ; Timer/Counter0 Overflow
000007 9518 reti ; USART0, Rx Complete
000008 9518 reti ; USART0 Data Register Empty
000009 9518 reti ; USART0, Tx Complete
00000a 9518 reti ; Analog Comparator
00000b 9518 reti ; Change Interrupt Request 0
00000c 9518 reti ; Timer/Counter1 Compare Match B
00000d 9518 reti ; Timer/Counter0 Compare Match A
00000e 9518 reti ; Timer/Counter0 Compare Match B
00000f 9518 reti ; USI Start Condition
000010 9518 reti ; USI Overflow
000011 9518 reti ; EEPROM Ready
000012 c002 rjmp WDT_vect ; Watchdog Timer Overflow
000013 9518 reti ; Change Interrupt Request 1
000014 9518 reti ; Change Interrupt Request 2
WDT_vect:
000015 94a3 inc wdt_counter
000016 d01e rcall toggle_led
000017 b501 in temp_r, WDTCSR
000018 6400 ori temp_r, (1<<WDIE)
000019 bd01 out WDTCSR, temp_r
00001a 9518 reti
RESET_vect:
00001b ed0f ldi temp_r, low(RAMEND)
; setup stack pointer
00001c bf0d out SPL, temp_r
00001d d010 rcall init_ports
00001e d002 rcall init_sm
00001f d005 rcall init_wdt
; go to main loop
000020 c012 rjmp loop
; config sleep mode to power-down
init_sm:
000021 b705 in temp_r, MCUCR
000022 6100 ori temp_r, (1<<SM0)
000023 bf05 out MCUCR, temp_r
000024 9508 ret
; config watchdog to interrupt mode
init_wdt:
000025 94f8 cli
000026 95a8 wdr
000027 b501 in temp_r, WDTCSR
000028 6108 ori temp_r, (1<<WDCE) | (1<<WDE)
; allow changing the watchdog bits and enable watchdog
000029 bd01 out WDTCSR, temp_r
00002a e40e ldi temp_r, (1<<WDE) | (1<<WDIE) | (1<<WDP2) | (1<<WDP1)
; config watchdog to interrupt mode and setup prescaler 512K cycles (4 sec)
00002b bd01 out WDTCSR, temp_r
00002c 9478 sei
00002d 9508 ret
init_ports:
00002e ef0f ldi temp_r, 0xff
00002f bb0a out DDRA, temp_r
000030 2700 clr temp_r
000031 bb0b out PORTA, temp_r
000032 9508 ret
; main program loop
loop:
000033 d006 rcall wdt_sleep_check
000034 cffe rjmp loop
toggle_led:
000035 9ad8 sbi PORTA, PA0
000036 d01b rcall delay_100ms
000037 98d8 cbi PORTA, PA0
000038 d019 rcall delay_100ms
000039 9508 ret
wdt_sleep_check:
; how many seconds should elapse before entering sleep mode,
; subject to a prescaler of 128K cycles (1 sec)
.equ delay_seconds = 10
00003a 930f push r16
00003b e00a ldi r16, delay_seconds
00003c 16a0 cp wdt_counter, r16
00003d f408 brsh _mcu_sleep
00003e c008 rjmp _sleep_exit
_mcu_sleep:
00003f 24aa clr wdt_counter
000040 d008 rcall WDT_off
000041 b705 in temp_r, MCUCR
000042 6200 ori temp_r, (1<<SE)
000043 bf05 out MCUCR, temp_r
000044 910f pop r16
000045 94f8 cli
000046 9588 sleep
_sleep_exit:
000047 910f pop r16
000048 9508 ret
WDT_off:
000049 95a8 wdr
; clear WDRF in MCUSR
00004a e000 ldi temp_r, (0<<WDRF)
00004b bf04 out MCUSR, r16
; write logical one to WDCE and WDE
; keep old prescaler setting to prevent unintentional Watchdog Reset
00004c b501 in temp_r, WDTCSR
00004d 6108 ori temp_r, (1<<WDCE) | (1<<WDE)
00004e bd01 out WDTCSR, temp_r
; turn off WDT
00004f e000 ldi temp_r, (0<<WDE)
000050 bd01 out WDTCSR, temp_r
000051 9508 ret
delay_100ms: ; For 1MHz frequency
000052 e822 ldi r18, 130
000053 ed3c ldi r19, 220
_loop_d_100ms:
000054 953a dec r19
000055 f7f1 brne _loop_d_100ms
000056 952a dec r18
000057 f7e1 brne _loop_d_100ms
000058 0000 nop
000059 9508 ret
RESOURCE USE INFORMATION
------------------------
Notice:
The register and instruction counts are symbol table hit counts,
and hence implicitly used resources are not counted, eg, the
'lpm' instruction without operands implicitly uses r0 and z,
none of which are counted.
x,y,z are separate entities in the symbol table and are
counted separately from r26..r31 here.
.dseg memory usage only counts static data declared with .byte
"ATtiny2313A" register use summary:
x : 0 y : 0 z : 0 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 3 r11: 0 r12: 0
r13: 0 r14: 0 r15: 0 r16: 32 r17: 0 r18: 2 r19: 2 r20: 0
r21: 0 r22: 0 r23: 0 r24: 0 r25: 0 r26: 0 r27: 0 r28: 0
r29: 0 r30: 0 r31: 0
Registers used: 4 out of 35 (11.4%)
"ATtiny2313A" instruction use summary:
.lds : 0 .sts : 0 adc : 0 add : 0 adiw : 0 and : 0
andi : 0 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
brcc : 0 brcs : 0 break : 0 breq : 0 brge : 0 brhc : 0
brhs : 0 brid : 0 brie : 0 brlo : 0 brlt : 0 brmi : 0
brne : 2 brpl : 0 brsh : 1 brtc : 0 brts : 0 brvc : 0
brvs : 0 bset : 0 bst : 0 cbi : 1 cbr : 0 clc : 0
clh : 0 cli : 2 cln : 0 clr : 2 cls : 0 clt : 0
clv : 0 clz : 0 com : 0 cp : 1 cpc : 0 cpi : 0
cpse : 0 dec : 2 eor : 0 icall : 0 ijmp : 0 in : 5
inc : 1 ld : 0 ldd : 0 ldi : 8 lds : 0 lpm : 0
lsl : 0 lsr : 0 mov : 0 movw : 0 neg : 0 nop : 1
or : 0 ori : 5 out : 11 pop : 2 push : 1 rcall : 8
ret : 7 reti : 20 rjmp : 5 rol : 0 ror : 0 sbc : 0
sbci : 0 sbi : 1 sbic : 0 sbis : 0 sbiw : 0 sbr : 0
sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 1 sen : 0
ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 1
spm : 0 st : 0 std : 0 sts : 0 sub : 0 subi : 0
swap : 0 tst : 0 wdr : 2
Instructions used: 23 out of 105 (21.9%)
"ATtiny2313A" memory use summary [bytes]:
Segment Begin End Code Data Used Size Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x0000b4 180 0 180 2048 8.8%
[.dseg] 0x000060 0x000060 0 0 0 128 0.0%
[.eseg] 0x000000 0x000000 0 0 0 128 0.0%
Assembly complete, 0 errors, 0 warnings

496
dist/default/production/attiny2313a_sleep-mode-example.X.production.map vendored Normal file
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@ -0,0 +1,496 @@
AVRASM ver. 2.2.7 firmware.asm Sun May 29 00:54:54 2022
EQU SIGNATURE_000 0000001e
EQU SIGNATURE_001 00000091
EQU SIGNATURE_002 0000000a
EQU SREG 0000003f
EQU SPL 0000003d
EQU OCR0B 0000003c
EQU GIMSK 0000003b
EQU EIFR 0000003a
EQU TIMSK 00000039
EQU TIFR 00000038
EQU SPMCSR 00000037
EQU OCR0A 00000036
EQU MCUCR 00000035
EQU MCUSR 00000034
EQU TCCR0B 00000033
EQU TCNT0 00000032
EQU OSCCAL 00000031
EQU TCCR0A 00000030
EQU TCCR1A 0000002f
EQU TCCR1B 0000002e
EQU TCNT1L 0000002c
EQU TCNT1H 0000002d
EQU OCR1AL 0000002a
EQU OCR1AH 0000002b
EQU OCR1BL 00000028
EQU OCR1BH 00000029
EQU CLKPR 00000026
EQU ICR1L 00000024
EQU ICR1H 00000025
EQU GTCCR 00000023
EQU TCCR1C 00000022
EQU WDTCR 00000021
EQU PCMSK0 00000020
EQU EEAR 0000001e
EQU EEDR 0000001d
EQU EECR 0000001c
EQU PORTA 0000001b
EQU DDRA 0000001a
EQU PINA 00000019
EQU PORTB 00000018
EQU DDRB 00000017
EQU PINB 00000016
EQU GPIOR2 00000015
EQU GPIOR1 00000014
EQU GPIOR0 00000013
EQU PORTD 00000012
EQU DDRD 00000011
EQU PIND 00000010
EQU USIDR 0000000f
EQU USISR 0000000e
EQU USICR 0000000d
EQU UDR 0000000c
EQU UCSRA 0000000b
EQU UCSRB 0000000a
EQU UBRRL 00000009
EQU ACSR 00000008
EQU BODCR 00000007
EQU PRR 00000006
EQU PCMSK2 00000005
EQU PCMSK1 00000004
EQU UCSRC 00000003
EQU UBRRH 00000002
EQU DIDR 00000001
EQU PORTB0 00000000
EQU PB0 00000000
EQU PORTB1 00000001
EQU PB1 00000001
EQU PORTB2 00000002
EQU PB2 00000002
EQU PORTB3 00000003
EQU PB3 00000003
EQU PORTB4 00000004
EQU PB4 00000004
EQU PORTB5 00000005
EQU PB5 00000005
EQU PORTB6 00000006
EQU PB6 00000006
EQU PORTB7 00000007
EQU PB7 00000007
EQU DDB0 00000000
EQU DDB1 00000001
EQU DDB2 00000002
EQU DDB3 00000003
EQU DDB4 00000004
EQU DDB5 00000005
EQU DDB6 00000006
EQU DDB7 00000007
EQU PINB0 00000000
EQU PINB1 00000001
EQU PINB2 00000002
EQU PINB3 00000003
EQU PINB4 00000004
EQU PINB5 00000005
EQU PINB6 00000006
EQU PINB7 00000007
EQU OCIE0A 00000000
EQU TOIE0 00000001
EQU OCIE0B 00000002
EQU OCF0A 00000000
EQU TOV0 00000001
EQU OCF0B 00000002
EQU OCR0_0 00000000
EQU OCR0_1 00000001
EQU OCR0_2 00000002
EQU OCR0_3 00000003
EQU OCR0_4 00000004
EQU OCR0_5 00000005
EQU OCR0_6 00000006
EQU OCR0_7 00000007
EQU OCR0A_0 00000000
EQU OCR0A_1 00000001
EQU OCR0A_2 00000002
EQU OCR0A_3 00000003
EQU OCR0A_4 00000004
EQU OCR0A_5 00000005
EQU OCR0A_6 00000006
EQU OCR0A_7 00000007
EQU WGM00 00000000
EQU WGM01 00000001
EQU COM0B0 00000004
EQU COM0B1 00000005
EQU COM0A0 00000006
EQU COM0A1 00000007
EQU TCNT0_0 00000000
EQU TCNT0_1 00000001
EQU TCNT0_2 00000002
EQU TCNT0_3 00000003
EQU TCNT0_4 00000004
EQU TCNT0_5 00000005
EQU TCNT0_6 00000006
EQU TCNT0_7 00000007
EQU TCCR0 00000033
EQU CS00 00000000
EQU CS01 00000001
EQU CS02 00000002
EQU WGM02 00000003
EQU FOC0B 00000006
EQU FOC0A 00000007
EQU ICIE1 00000003
EQU TICIE 00000003
EQU OCIE1B 00000005
EQU OCIE1A 00000006
EQU TOIE1 00000007
EQU ICF1 00000003
EQU OCF1B 00000005
EQU OCF1A 00000006
EQU TOV1 00000007
EQU WGM10 00000000
EQU PWM10 00000000
EQU WGM11 00000001
EQU PWM11 00000001
EQU COM1B0 00000004
EQU COM1B1 00000005
EQU COM1A0 00000006
EQU COM1A1 00000007
EQU CS10 00000000
EQU CS11 00000001
EQU CS12 00000002
EQU WGM12 00000003
EQU CTC1 00000003
EQU WGM13 00000004
EQU ICES1 00000006
EQU ICNC1 00000007
EQU FOC1B 00000006
EQU FOC1A 00000007
EQU WDTCSR 00000021
EQU WDP0 00000000
EQU WDP1 00000001
EQU WDP2 00000002
EQU WDE 00000003
EQU WDCE 00000004
EQU WDTOE 00000004
EQU WDP3 00000005
EQU WDIE 00000006
EQU WDIF 00000007
EQU UDR0 00000000
EQU UDR1 00000001
EQU UDR2 00000002
EQU UDR3 00000003
EQU UDR4 00000004
EQU UDR5 00000005
EQU UDR6 00000006
EQU UDR7 00000007
EQU USR 0000000b
EQU MPCM 00000000
EQU U2X 00000001
EQU UPE 00000002
EQU PE 00000002
EQU DOR 00000003
EQU FE 00000004
EQU UDRE 00000005
EQU TXC 00000006
EQU RXC 00000007
EQU UCR 0000000a
EQU TXB8 00000000
EQU RXB8 00000001
EQU UCSZ2 00000002
EQU CHR9 00000002
EQU TXEN 00000003
EQU RXEN 00000004
EQU UDRIE 00000005
EQU TXCIE 00000006
EQU RXCIE 00000007
EQU UCPOL 00000000
EQU UCSZ0 00000001
EQU UCSZ1 00000002
EQU USBS 00000003
EQU UPM0 00000004
EQU UPM1 00000005
EQU UMSEL0 00000006
EQU UMSEL1 00000007
EQU UCPHA 00000001
EQU UDORD 00000002
EQU UBRR 00000009
EQU ACIS0 00000000
EQU ACIS1 00000001
EQU ACIC 00000002
EQU ACIE 00000003
EQU ACI 00000004
EQU ACO 00000005
EQU ACBG 00000006
EQU ACD 00000007
EQU AIN0D 00000000
EQU AIN1D 00000001
EQU PORTD0 00000000
EQU PD0 00000000
EQU PORTD1 00000001
EQU PD1 00000001
EQU PORTD2 00000002
EQU PD2 00000002
EQU PORTD3 00000003
EQU PD3 00000003
EQU PORTD4 00000004
EQU PD4 00000004
EQU PORTD5 00000005
EQU PD5 00000005
EQU PORTD6 00000006
EQU PD6 00000006
EQU DDD0 00000000
EQU DDD1 00000001
EQU DDD2 00000002
EQU DDD3 00000003
EQU DDD4 00000004
EQU DDD5 00000005
EQU DDD6 00000006
EQU PIND0 00000000
EQU PIND1 00000001
EQU PIND2 00000002
EQU PIND3 00000003
EQU PIND4 00000004
EQU PIND5 00000005
EQU PIND6 00000006
EQU EEARL 0000001e
EQU EEAR0 00000000
EQU EEAR1 00000001
EQU EEAR2 00000002
EQU EEAR3 00000003
EQU EEAR4 00000004
EQU EEAR5 00000005
EQU EEAR6 00000006
EQU EEDR0 00000000
EQU EEDR1 00000001
EQU EEDR2 00000002
EQU EEDR3 00000003
EQU EEDR4 00000004
EQU EEDR5 00000005
EQU EEDR6 00000006
EQU EEDR7 00000007
EQU EERE 00000000
EQU EEPE 00000001
EQU EEWE 00000001
EQU EEMPE 00000002
EQU EEMWE 00000002
EQU EERIE 00000003
EQU EEPM0 00000004
EQU EEPM1 00000005
EQU PORTA0 00000000
EQU PA0 00000000
EQU PORTA1 00000001
EQU PA1 00000001
EQU PORTA2 00000002
EQU PA2 00000002
EQU DDA0 00000000
EQU DDA1 00000001
EQU DDA2 00000002
EQU PINA0 00000000
EQU PINA1 00000001
EQU PINA2 00000002
EQU USIDR0 00000000
EQU USIDR1 00000001
EQU USIDR2 00000002
EQU USIDR3 00000003
EQU USIDR4 00000004
EQU USIDR5 00000005
EQU USIDR6 00000006
EQU USIDR7 00000007
EQU USICNT0 00000000
EQU USICNT1 00000001
EQU USICNT2 00000002
EQU USICNT3 00000003
EQU USIDC 00000004
EQU USIPF 00000005
EQU USIOIF 00000006
EQU USISIF 00000007
EQU USITC 00000000
EQU USICLK 00000001
EQU USICS0 00000002
EQU USICS1 00000003
EQU USIWM0 00000004
EQU USIWM1 00000005
EQU USIOIE 00000006
EQU USISIE 00000007
EQU PCIE1 00000003
EQU PCIE2 00000004
EQU PCIE0 00000005
EQU INT0 00000006
EQU INT1 00000007
EQU GIFR 0000003a
EQU PCIF0 00000005
EQU PCIF2 00000004
EQU PCIF1 00000003
EQU INTF0 00000006
EQU INTF1 00000007
EQU PCINT11 00000000
EQU PCINT12 00000001
EQU PCINT13 00000002
EQU PCINT14 00000003
EQU PCINT15 00000004
EQU PCINT16 00000005
EQU PCINT17 00000006
EQU PCINT8 00000000
EQU PCINT9 00000001
EQU PCINT10 00000002
EQU SREG_C 00000000
EQU SREG_Z 00000001
EQU SREG_N 00000002
EQU SREG_V 00000003
EQU SREG_S 00000004
EQU SREG_H 00000005
EQU SREG_T 00000006
EQU SREG_I 00000007
EQU SPMEN 00000000
EQU PGERS 00000001
EQU PGWRT 00000002
EQU RFLB 00000003
EQU CTPB 00000004
EQU ISC00 00000000
EQU ISC01 00000001
EQU ISC10 00000002
EQU ISC11 00000003
EQU SM0 00000004
EQU SM 00000004
EQU SE 00000005
EQU SM1 00000006
EQU PUD 00000007
EQU CLKPS0 00000000
EQU CLKPS1 00000001
EQU CLKPS2 00000002
EQU CLKPS3 00000003
EQU CLKPCE 00000007
EQU PORF 00000000
EQU EXTRF 00000001
EQU BORF 00000002
EQU WDRF 00000003
EQU CAL0 00000000
EQU CAL1 00000001
EQU CAL2 00000002
EQU CAL3 00000003
EQU CAL4 00000004
EQU CAL5 00000005
EQU CAL6 00000006
EQU SFIOR 00000023
EQU PSR10 00000000
EQU PCINT0 00000000
EQU PCINT1 00000001
EQU PCINT2 00000002
EQU PCINT3 00000003
EQU PCINT4 00000004
EQU PCINT5 00000005
EQU PCINT6 00000006
EQU PCINT7 00000007
EQU GPIOR20 00000000
EQU GPIOR21 00000001
EQU GPIOR22 00000002
EQU GPIOR23 00000003
EQU GPIOR24 00000004
EQU GPIOR25 00000005
EQU GPIOR26 00000006
EQU GPIOR27 00000007
EQU GPIOR10 00000000
EQU GPIOR11 00000001
EQU GPIOR12 00000002
EQU GPIOR13 00000003
EQU GPIOR14 00000004
EQU GPIOR15 00000005
EQU GPIOR16 00000006
EQU GPIOR17 00000007
EQU GPIOR00 00000000
EQU GPIOR01 00000001
EQU GPIOR02 00000002
EQU GPIOR03 00000003
EQU GPIOR04 00000004
EQU GPIOR05 00000005
EQU GPIOR06 00000006
EQU GPIOR07 00000007
EQU PRUSART 00000000
EQU PRUSI 00000001
EQU PRTIM0 00000002
EQU PRTIM1 00000003
EQU BPDSE 00000000
EQU BPDS 00000001
EQU LB1 00000000
EQU LB2 00000001
EQU CKSEL0 00000000
EQU CKSEL1 00000001
EQU CKSEL2 00000002
EQU CKSEL3 00000003
EQU SUT0 00000004
EQU SUT1 00000005
EQU CKOUT 00000006
EQU CKDIV8 00000007
EQU BODLEVEL0 00000000
EQU BODLEVEL1 00000001
EQU BODLEVEL2 00000002
EQU EESAVE 00000003
EQU WDTON 00000004
EQU SPIEN 00000005
EQU DWEN 00000006
EQU RSTDISBL 00000007
EQU SELFPRGEN 00000000
DEF XH r27
DEF XL r26
DEF YH r29
DEF YL r28
DEF ZH r31
DEF ZL r30
EQU FLASHEND 000003ff
EQU IOEND 0000003f
EQU SRAM_START 00000060
EQU SRAM_SIZE 00000080
EQU RAMEND 000000df
EQU XRAMEND 00000000
EQU E2END 0000007f
EQU EEPROMEND 0000007f
EQU EEADRBITS 00000007
EQU NRWW_START_ADDR 00000000
EQU NRWW_STOP_ADDR 000003ff
EQU RWW_START_ADDR 00000000
EQU RWW_STOP_ADDR 00000000
EQU PAGESIZE 00000010
EQU INT0addr 00000001
EQU INT1addr 00000002
EQU ICP1addr 00000003
EQU OC1Aaddr 00000004
EQU OC1addr 00000004
EQU OVF1addr 00000005
EQU OVF0addr 00000006
EQU URXCaddr 00000007
EQU URXC0addr 00000007
EQU UDREaddr 00000008
EQU UDRE0addr 00000008
EQU UTXCaddr 00000009
EQU UTXC0addr 00000009
EQU ACIaddr 0000000a
EQU PCIBaddr 0000000b
EQU PCIaddr 0000000b
EQU OC1Baddr 0000000c
EQU OC0Aaddr 0000000d
EQU OC0Baddr 0000000e
EQU USI_STARTaddr 0000000f
EQU USI_OVFaddr 00000010
EQU ERDYaddr 00000011
EQU WDTaddr 00000012
EQU PCIAaddr 00000013
EQU PCIDaddr 00000014
EQU INT_VECTORS_SIZE 00000015
DEF temp_r r16
DEF wdt_counter r10
CSEG RESET_vect 0000001b
CSEG WDT_vect 00000015
CSEG toggle_led 00000035
CSEG init_ports 0000002e
CSEG init_sm 00000021
CSEG init_wdt 00000025
CSEG loop 00000033
CSEG wdt_sleep_check 0000003a
CSEG delay_100ms 00000052
EQU delay_seconds 0000000a
CSEG _mcu_sleep 0000003f
CSEG _sleep_exit 00000047
CSEG WDT_off 00000049
CSEG _loop_d_100ms 00000054

BIN
dist/default/production/attiny2313a_sleep-mode-example.X.production.obj vendored Normal file
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Binary file not shown.

38
dist/default/production/attiny2313a_sleep-mode-example.X.production.tmp vendored Normal file
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<ASSEMBLER_INFO>
<VERSION>2.2.7</VERSION>
<DEVICE>"ATtiny2313A"</DEVICE>
<WORKING_DIR>D:\Apps\attiny2313a_sleep-mode-example.X</WORKING_DIR>
<INCLUDE_PATH>
<DIR>C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc</DIR>
<DIR>C:\Program Files (x86)\Atmel\AVR Tools\AvrAssembler2\Appnotes</DIR>
</INCLUDE_PATH>
<SOURCE_FILE>firmware.asm</SOURCE_FILE>
<INCLUDED_FILES>
<FILE>C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn2313Adef.inc</FILE>
</INCLUDED_FILES>
<OBJECT_FILES>
<FILE>dist/default/production/attiny2313a_sleep-mode-example.X.production.obj</FILE>
</OBJECT_FILES>
<HEX_FILES>
<FILE>dist/default/production/attiny2313a_sleep-mode-example.X.production.hex</FILE>
</HEX_FILES>
<OUTPUT_FILES>
<FILE>dist/default/production/attiny2313a_sleep-mode-example.X.production.map</FILE>
<FILE>dist/default/production/attiny2313a_sleep-mode-example.X.production.lss</FILE>
</OUTPUT_FILES>
<LABELS>
<RESET_vect><FILE>firmware.asm</FILE><LINE>54</LINE></RESET_vect>
<WDT_vect><FILE>firmware.asm</FILE><LINE>46</LINE></WDT_vect>
<toggle_led><FILE>firmware.asm</FILE><LINE>101</LINE></toggle_led>
<init_ports><FILE>firmware.asm</FILE><LINE>89</LINE></init_ports>
<init_sm><FILE>firmware.asm</FILE><LINE>67</LINE></init_sm>
<init_wdt><FILE>firmware.asm</FILE><LINE>74</LINE></init_wdt>
<loop><FILE>firmware.asm</FILE><LINE>97</LINE></loop>
<wdt_sleep_check><FILE>firmware.asm</FILE><LINE>108</LINE></wdt_sleep_check>
<delay_100ms><FILE>firmware.asm</FILE><LINE>145</LINE></delay_100ms>
<_mcu_sleep><FILE>firmware.asm</FILE><LINE>117</LINE></_mcu_sleep>
<_sleep_exit><FILE>firmware.asm</FILE><LINE>126</LINE></_sleep_exit>
<WDT_off><FILE>firmware.asm</FILE><LINE>130</LINE></WDT_off>
<_loop_d_100ms><FILE>firmware.asm</FILE><LINE>149</LINE></_loop_d_100ms>
</LABELS>
</ASSEMBLER_INFO>

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:020000020000FC
:100000001AC018951895189518951895189518955B
:100010001895189518951895189518951895189578
:100020001895189518951895189513951CD001B525
:10003000006401BD18950FED0DBF0ED012C005B7BD
:10004000006405BF0895F894A89501B5086101BD45
:100050000CE401BD789408950FEF0ABB00270BBB99
:10006000089501D0FECFD89A0CD0D8980AD0089520
:10007000A89500E004BF01B5086101BD00E001BD25
:10008000089522E83CED3A95F1F72A95E1F7000052
:020090000895D1
:00000001FF

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nbproject/Makefile-default.mk Normal file
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#
# Generated Makefile - do not edit!
#
# Edit the Makefile in the project folder instead (../Makefile). Each target
# has a -pre and a -post target defined where you can add customized code.
#
# This makefile implements configuration specific macros and targets.
# Include project Makefile
ifeq "${IGNORE_LOCAL}" "TRUE"
# do not include local makefile. User is passing all local related variables already
else
include Makefile
# Include makefile containing local settings
ifeq "$(wildcard nbproject/Makefile-local-default.mk)" "nbproject/Makefile-local-default.mk"
include nbproject/Makefile-local-default.mk
endif
endif
# Environment
MKDIR=gnumkdir -p
RM=rm -f
MV=mv
CP=cp
# Macros
CND_CONF=default
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
IMAGE_TYPE=debug
OUTPUT_SUFFIX=obj
DEBUGGABLE_SUFFIX=obj
FINAL_IMAGE=${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
else
IMAGE_TYPE=production
OUTPUT_SUFFIX=obj
DEBUGGABLE_SUFFIX=obj
FINAL_IMAGE=${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
endif
ifeq ($(COMPARE_BUILD), true)
COMPARISON_BUILD=
else
COMPARISON_BUILD=
endif
ifdef SUB_IMAGE_ADDRESS
else
SUB_IMAGE_ADDRESS_COMMAND=
endif
# Object Directory
OBJECTDIR=build/${CND_CONF}/${IMAGE_TYPE}
# Distribution Directory
DISTDIR=dist/${CND_CONF}/${IMAGE_TYPE}
# Source Files Quoted if spaced
SOURCEFILES_QUOTED_IF_SPACED=firmware.asm
# Object Files Quoted if spaced
OBJECTFILES_QUOTED_IF_SPACED=${OBJECTDIR}/firmware.obj
POSSIBLE_DEPFILES=${OBJECTDIR}/firmware.obj.d
# Object Files
OBJECTFILES=${OBJECTDIR}/firmware.obj
# Source Files
SOURCEFILES=firmware.asm
# Pack Options
PACK_ASSEMBLER_OPTIONS=-I "${DFP_DIR}/avrasm/inc" -i tn2313Adef.inc
CFLAGS=
ASFLAGS=
LDLIBSOPTIONS=
############# Tool locations ##########################################
# If you copy a project from one host to another, the path where the #
# compiler is installed may be different. #
# If you open this project with MPLAB X in the new host, this #
# makefile will be regenerated and the paths will be corrected. #
#######################################################################
# fixDeps replaces a bunch of sed/cat/printf statements that slow down the build
FIXDEPS=fixDeps
.build-conf: ${BUILD_SUBPROJECTS}
ifneq ($(INFORMATION_MESSAGE), )
@echo $(INFORMATION_MESSAGE)
endif
${MAKE} -f nbproject/Makefile-default.mk ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
# ------------------------------------------------------------------------------------
# Rules for buildStep: assemble
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
${OBJECTDIR}/firmware.obj: firmware.asm nbproject/Makefile-${CND_CONF}.mk
@${MKDIR} ${DISTDIR}
@${MKDIR} "${OBJECTDIR}"
@${RM} ${OBJECTDIR}/firmware.obj
${MP_AS} -fI -W+ie ${PACK_ASSEMBLER_OPTIONS} -d ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} -m ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.map -S ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.tmp firmware.asm
else
${OBJECTDIR}/firmware.obj: firmware.asm nbproject/Makefile-${CND_CONF}.mk
@${MKDIR} ${DISTDIR}
@${MKDIR} "${OBJECTDIR}"
@${RM} ${OBJECTDIR}/firmware.obj
${MP_AS} -fI -W+ie ${PACK_ASSEMBLER_OPTIONS} -d ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} -S ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.tmp -o ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.hex -m ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.map -l ${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.lss firmware.asm
endif
# ------------------------------------------------------------------------------------
# Rules for buildStep: link
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk
else
${DISTDIR}/attiny2313a_sleep-mode-example.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk
endif
# Subprojects
.build-subprojects:
# Subprojects
.clean-subprojects:
# Clean Targets
.clean-conf: ${CLEAN_SUBPROJECTS}
${RM} -r ${OBJECTDIR}
${RM} -r ${DISTDIR}
# Enable dependency checking
.dep.inc: .depcheck-impl
DEPFILES=$(shell mplabwildcard ${POSSIBLE_DEPFILES})
ifneq (${DEPFILES},)
include ${DEPFILES}
endif

14
nbproject/Makefile-genesis.properties Normal file
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#
#Fri May 27 22:24:34 MSK 2022
default.languagetoolchain.version=2.2.7
default.Pack.dfplocation=C\:\\Users\\\u0421\u0435\u0440\u0433\u0435\u0439\\.mchp_packs\\Microchip\\ATtiny_DFP\\3.0.151
default.com-microchip-mplab-mdbcore-simulator-Simulator.md5=19e4dc0f223322f74cda227c3c12c71c
conf.ids=default
default.languagetoolchain.dir=D\:\\avrasm2
host.id=1aqy-hj7k-bx
configurations-xml=31f5f7f3709f73e27515fde1256b18c8
default.com-microchip-mplab-nbide-toolchain-avrasm-AVRASMLanguageToolchain.md5=0e94da8ed93e9650ffef50929833a79f
com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=6e02ca5e9f5042ffd365b42ab82d3a9b
user-defined-mime-resolver-xml=none
proj.dir=D\:\\Apps\\attiny2313a_sleep-mode-example.X
host.platform=windows

69
nbproject/Makefile-impl.mk Normal file
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#
# Generated Makefile - do not edit!
#
# Edit the Makefile in the project folder instead (../Makefile). Each target
# has a pre- and a post- target defined where you can add customization code.
#
# This makefile implements macros and targets common to all configurations.
#
# NOCDDL
# Building and Cleaning subprojects are done by default, but can be controlled with the SUB
# macro. If SUB=no, subprojects will not be built or cleaned. The following macro
# statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf
# and .clean-reqprojects-conf unless SUB has the value 'no'
SUB_no=NO
SUBPROJECTS=${SUB_${SUB}}
BUILD_SUBPROJECTS_=.build-subprojects
BUILD_SUBPROJECTS_NO=
BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}}
CLEAN_SUBPROJECTS_=.clean-subprojects
CLEAN_SUBPROJECTS_NO=
CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}}
# Project Name
PROJECTNAME=attiny2313a_sleep-mode-example.X
# Active Configuration
DEFAULTCONF=default
CONF=${DEFAULTCONF}
# All Configurations
ALLCONFS=default
# build
.build-impl: .build-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-conf
# clean
.clean-impl: .clean-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .clean-conf
# clobber
.clobber-impl: .clobber-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default clean
# all
.all-impl: .all-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default build
# dependency checking support
.depcheck-impl:
# @echo "# This code depends on make tool being used" >.dep.inc
# @if [ -n "${MAKE_VERSION}" ]; then \
# echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \
# echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \
# echo "include \$${DEPFILES}" >>.dep.inc; \
# echo "endif" >>.dep.inc; \
# else \
# echo ".KEEP_STATE:" >>.dep.inc; \
# echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \
# fi

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#
# Generated Makefile - do not edit!
#
#
# This file contains information about the location of compilers and other tools.
# If you commmit this file into your revision control server, you will be able to
# to checkout the project and build it from the command line with make. However,
# if more than one person works on the same project, then this file might show
# conflicts since different users are bound to have compilers in different places.
# In that case you might choose to not commit this file and let MPLAB X recreate this file
# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at
# least once so the file gets created and the project can be built. Finally, you can also
# avoid using this file at all if you are only building from the command line with make.
# You can invoke make with the values of the macros:
# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ...
#
SHELL=cmd.exe
PATH_TO_IDE_BIN=C:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/
# Adding MPLAB X bin directory to path.
PATH:=C:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/:$(PATH)
# Path to java used to run MPLAB X when this makefile was created
MP_JAVA_PATH="C:\Program Files\Microchip\MPLABX\v6.00\sys\java\zulu8.54.0.21-ca-fx-jre8.0.292-win_x64/bin/"
OS_CURRENT="$(shell uname -s)"
# MP_CC is not defined
# MP_CPPC is not defined
# MP_BC is not defined
MP_AS="D:\avrasm2\avrasm2.exe"
# MP_LD is not defined
# MP_AR is not defined
DEP_GEN=${MP_JAVA_PATH}java -jar "C:/Program Files/Microchip/MPLABX/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/extractobjectdependencies.jar"
# MP_CC_DIR is not defined
# MP_CPPC_DIR is not defined
# MP_BC_DIR is not defined
MP_AS_DIR="D:\avrasm2"
# MP_LD_DIR is not defined
# MP_AR_DIR is not defined
# MP_BC_DIR is not defined
DFP_DIR=C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151

10
nbproject/Makefile-variables.mk Normal file
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@ -0,0 +1,10 @@
#
# Generated - do not edit!
#
# NOCDDL
#
CND_BASEDIR=`pwd`
# default configuration
CND_ARTIFACT_DIR_default=dist/default/production
CND_ARTIFACT_NAME_default=attiny2313a_sleep-mode-example.X.production.obj
CND_ARTIFACT_PATH_default=dist/default/production/attiny2313a_sleep-mode-example.X.production.obj

1017
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25
nbproject/private/configurations.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<configurationDescriptor version="65">
<projectmakefile>Makefile</projectmakefile>
<defaultConf>0</defaultConf>
<confs>
<conf name="default" type="2">
<platformToolSN></platformToolSN>
<languageToolchainDir>D:\avrasm2</languageToolchainDir>
<mdbdebugger version="1">
<placeholder1>place holder 1</placeholder1>
<placeholder2>place holder 2</placeholder2>
</mdbdebugger>
<runprofile version="6">
<args></args>
<rundir></rundir>
<buildfirst>true</buildfirst>
<console-type>0</console-type>
<terminal-type>0</terminal-type>
<remove-instrumentation>0</remove-instrumentation>
<environment>
</environment>
</runprofile>
</conf>
</confs>
</configurationDescriptor>

27
nbproject/project.xml Normal file
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@ -0,0 +1,27 @@
<?xml version="1.0" encoding="UTF-8"?>
<project xmlns="http://www.netbeans.org/ns/project/1">
<type>com.microchip.mplab.nbide.embedded.makeproject</type>
<configuration>
<data xmlns="http://www.netbeans.org/ns/make-project/1">
<name>attiny2313a_sleep-mode-example</name>
<creation-uuid>9f8fede7-8e3c-4ec2-b472-dce08c1ae1ab</creation-uuid>
<make-project-type>0</make-project-type>
<c-extensions/>
<cpp-extensions/>
<header-extensions/>
<asminc-extensions/>
<sourceEncoding>ISO-8859-1</sourceEncoding>
<make-dep-projects/>
<sourceRootList/>
<confList>
<confElem>
<name>default</name>
<type>2</type>
</confElem>
</confList>
<formatting>
<project-formatting-style>false</project-formatting-style>
</formatting>
</data>
</configuration>
</project>