mirror of
https://github.com/sergeyyarkov/attiny2313a_sleep-mode-example.git
synced 2026-10-11 10:18:53 +03:00
920 lines
57 KiB
Plaintext
920 lines
57 KiB
Plaintext
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AVRASM ver. 2.2.7 firmware.asm Sun May 29 00:54:54 2022
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[builtin](2): Including file 'C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn2313Adef.inc'
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[builtin](2): Including file 'C:/Users/Ñåðãåé/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn2313Adef.inc'
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;
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;***** Created: 2011-02-09 12:04 ******* Source: ATtiny2313A.xml *********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn2313Adef.inc"
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;* Title : Register/Bit Definitions for the ATtiny2313A
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny2313A
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN2313ADEF_INC_
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#define _TN2313ADEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny2313A
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#pragma AVRPART ADMIN PART_NAME ATtiny2313A
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x0a
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#pragma AVRPART CORE CORE_VERSION V2
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#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ OCR0B = 0x3c
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.equ GIMSK = 0x3b
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.equ EIFR = 0x3a
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.equ TIMSK = 0x39
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.equ TIFR = 0x38
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.equ SPMCSR = 0x37
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.equ OCR0A = 0x36
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0B = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ TCCR0A = 0x30
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.equ TCCR1A = 0x2f
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.equ TCCR1B = 0x2e
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.equ TCNT1L = 0x2c
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.equ TCNT1H = 0x2d
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.equ OCR1AL = 0x2a
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.equ OCR1AH = 0x2b
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.equ OCR1BL = 0x28
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.equ OCR1BH = 0x29
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.equ CLKPR = 0x26
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.equ ICR1L = 0x24
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.equ ICR1H = 0x25
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.equ GTCCR = 0x23
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.equ TCCR1C = 0x22
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.equ WDTCR = 0x21
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.equ PCMSK0 = 0x20
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.equ EEAR = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTA = 0x1b
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.equ DDRA = 0x1a
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.equ PINA = 0x19
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ GPIOR2 = 0x15
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.equ GPIOR1 = 0x14
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.equ GPIOR0 = 0x13
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.equ PORTD = 0x12
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.equ DDRD = 0x11
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.equ PIND = 0x10
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.equ USIDR = 0x0f
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.equ USISR = 0x0e
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.equ USICR = 0x0d
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.equ UDR = 0x0c
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.equ UCSRA = 0x0b
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.equ UCSRB = 0x0a
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.equ UBRRL = 0x09
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.equ ACSR = 0x08
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.equ BODCR = 0x07
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.equ PRR = 0x06
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.equ PCMSK2 = 0x05
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.equ PCMSK1 = 0x04
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.equ UCSRC = 0x03
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.equ UBRRH = 0x02
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.equ DIDR = 0x01
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; ***** BIT DEFINITIONS **************************************************
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; ***** PORTB ************************
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; PORTB - Port B Data Register
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.equ PORTB0 = 0 ; Port B Data Register bit 0
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ; Port B Data Register bit 1
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ; Port B Data Register bit 2
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ; Port B Data Register bit 3
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ; Port B Data Register bit 4
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ; Port B Data Register bit 5
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.equ PB5 = 5 ; For compatibility
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.equ PORTB6 = 6 ; Port B Data Register bit 6
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.equ PB6 = 6 ; For compatibility
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.equ PORTB7 = 7 ; Port B Data Register bit 7
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.equ PB7 = 7 ; For compatibility
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; DDRB - Port B Data Direction Register
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.equ DDB0 = 0 ; Port B Data Direction Register bit 0
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.equ DDB1 = 1 ; Port B Data Direction Register bit 1
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.equ DDB2 = 2 ; Port B Data Direction Register bit 2
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.equ DDB3 = 3 ; Port B Data Direction Register bit 3
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.equ DDB4 = 4 ; Port B Data Direction Register bit 4
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.equ DDB5 = 5 ; Port B Data Direction Register bit 5
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.equ DDB6 = 6 ; Port B Data Direction Register bit 6
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.equ DDB7 = 7 ; Port B Data Direction Register bit 7
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; PINB - Port B Input Pins
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.equ PINB0 = 0 ; Port B Input Pins bit 0
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.equ PINB1 = 1 ; Port B Input Pins bit 1
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.equ PINB2 = 2 ; Port B Input Pins bit 2
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.equ PINB3 = 3 ; Port B Input Pins bit 3
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.equ PINB4 = 4 ; Port B Input Pins bit 4
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.equ PINB5 = 5 ; Port B Input Pins bit 5
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.equ PINB6 = 6 ; Port B Input Pins bit 6
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.equ PINB7 = 7 ; Port B Input Pins bit 7
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; ***** TIMER_COUNTER_0 **************
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; TIMSK - Timer/Counter Interrupt Mask Register
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.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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; TIFR - Timer/Counter Interrupt Flag register
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.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
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.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
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.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
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; OCR0B - Timer/Counter0 Output Compare Register
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.equ OCR0_0 = 0 ;
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.equ OCR0_1 = 1 ;
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.equ OCR0_2 = 2 ;
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.equ OCR0_3 = 3 ;
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.equ OCR0_4 = 4 ;
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.equ OCR0_5 = 5 ;
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.equ OCR0_6 = 6 ;
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.equ OCR0_7 = 7 ;
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; OCR0A - Timer/Counter0 Output Compare Register
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.equ OCR0A_0 = 0 ;
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.equ OCR0A_1 = 1 ;
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.equ OCR0A_2 = 2 ;
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.equ OCR0A_3 = 3 ;
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.equ OCR0A_4 = 4 ;
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.equ OCR0A_5 = 5 ;
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.equ OCR0A_6 = 6 ;
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.equ OCR0A_7 = 7 ;
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; TCCR0A - Timer/Counter Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode
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.equ WGM01 = 1 ; Waveform Generation Mode
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.equ COM0B0 = 4 ; Compare Match Output B Mode
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.equ COM0B1 = 5 ; Compare Match Output B Mode
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.equ COM0A0 = 6 ; Compare Match Output A Mode
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.equ COM0A1 = 7 ; Compare Match Output A Mode
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; TCNT0 - Timer/Counter0
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.equ TCNT0_0 = 0 ;
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.equ TCNT0_1 = 1 ;
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.equ TCNT0_2 = 2 ;
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.equ TCNT0_3 = 3 ;
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.equ TCNT0_4 = 4 ;
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.equ TCNT0_5 = 5 ;
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.equ TCNT0_6 = 6 ;
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.equ TCNT0_7 = 7 ;
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; TCCR0B - Timer/Counter Control Register B
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.equ TCCR0 = TCCR0B ; For compatibility
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.equ CS00 = 0 ; Clock Select
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.equ CS01 = 1 ; Clock Select
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.equ CS02 = 2 ; Clock Select
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.equ WGM02 = 3 ;
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.equ FOC0B = 6 ; Force Output Compare B
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.equ FOC0A = 7 ; Force Output Compare B
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; ***** TIMER_COUNTER_1 **************
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; TIMSK - Timer/Counter Interrupt Mask Register
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.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
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.equ TICIE = ICIE1 ; For compatibility
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.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
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.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
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.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
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; TIFR - Timer/Counter Interrupt Flag register
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.equ ICF1 = 3 ; Input Capture Flag 1
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.equ OCF1B = 5 ; Output Compare Flag 1B
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.equ OCF1A = 6 ; Output Compare Flag 1A
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.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
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; TCCR1A - Timer/Counter1 Control Register A
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.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
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.equ PWM10 = WGM10 ; For compatibility
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.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
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.equ PWM11 = WGM11 ; For compatibility
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.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
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.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
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.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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; TCCR1B - Timer/Counter1 Control Register B
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.equ CS10 = 0 ; Clock Select bit 0
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.equ CS11 = 1 ; Clock Select 1 bit 1
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.equ CS12 = 2 ; Clock Select1 bit 2
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.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
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.equ CTC1 = WGM12 ; For compatibility
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.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
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.equ ICES1 = 6 ; Input Capture 1 Edge Select
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.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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; TCCR1C - Timer/Counter1 Control Register C
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.equ FOC1B = 6 ; Force Output Compare for Channel B
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.equ FOC1A = 7 ; Force Output Compare for Channel A
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; ***** WATCHDOG *********************
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; WDTCR - Watchdog Timer Control Register
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.equ WDTCSR = WDTCR ; For compatibility
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDCE = 4 ; Watchdog Change Enable
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.equ WDTOE = WDCE ; For compatibility
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.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
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.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
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; ***** USART ************************
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; UDR - USART I/O Data Register
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.equ UDR0 = 0 ; USART I/O Data Register bit 0
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.equ UDR1 = 1 ; USART I/O Data Register bit 1
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.equ UDR2 = 2 ; USART I/O Data Register bit 2
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.equ UDR3 = 3 ; USART I/O Data Register bit 3
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.equ UDR4 = 4 ; USART I/O Data Register bit 4
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.equ UDR5 = 5 ; USART I/O Data Register bit 5
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.equ UDR6 = 6 ; USART I/O Data Register bit 6
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.equ UDR7 = 7 ; USART I/O Data Register bit 7
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; UCSRA - USART Control and Status Register A
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.equ USR = UCSRA ; For compatibility
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.equ MPCM = 0 ; Multi-processor Communication Mode
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.equ U2X = 1 ; Double the USART Transmission Speed
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.equ UPE = 2 ; USART Parity Error
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.equ PE = UPE ; For compatibility
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.equ DOR = 3 ; Data overRun
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.equ FE = 4 ; Framing Error
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.equ UDRE = 5 ; USART Data Register Empty
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.equ TXC = 6 ; USART Transmitt Complete
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.equ RXC = 7 ; USART Receive Complete
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; UCSRB - USART Control and Status Register B
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.equ UCR = UCSRB ; For compatibility
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.equ TXB8 = 0 ; Transmit Data Bit 8
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.equ RXB8 = 1 ; Receive Data Bit 8
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.equ UCSZ2 = 2 ; Character Size
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.equ CHR9 = UCSZ2 ; For compatibility
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.equ TXEN = 3 ; Transmitter Enable
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.equ RXEN = 4 ; Receiver Enable
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.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
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.equ TXCIE = 6 ; TX Complete Interrupt Enable
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.equ RXCIE = 7 ; RX Complete Interrupt Enable
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; UCSRC - USART Control and Status Register C
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.equ UCPOL = 0 ; Clock Polarity
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.equ UCSZ0 = 1 ; Character Size Bit 0
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.equ UCSZ1 = 2 ; Character Size Bit 1
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.equ USBS = 3 ; Stop Bit Select
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.equ UPM0 = 4 ; Parity Mode Bit 0
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.equ UPM1 = 5 ; Parity Mode Bit 1
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.equ UMSEL0 = 6 ; USART Mode Select 0
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.equ UMSEL1 = 7 ; USART Mode Select 1
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.equ UCPHA = 1 ; USART MSPIM Clock Phase
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.equ UDORD = 2 ; USART MSPIM Data Order
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.equ UBRR = UBRRL ; For compatibility
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; ***** ANALOG_COMPARATOR ************
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ;
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ ACD = 7 ; Analog Comparator Disable
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; DIDR - Digital Input Disable Register 1
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.equ AIN0D = 0 ; AIN0 Digital Input Disable
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.equ AIN1D = 1 ; AIN1 Digital Input Disable
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; ***** PORTD ************************
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; PORTD - Data Register, Port D
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.equ PORTD0 = 0 ;
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.equ PD0 = 0 ; For compatibility
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.equ PORTD1 = 1 ;
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.equ PD1 = 1 ; For compatibility
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.equ PORTD2 = 2 ;
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.equ PD2 = 2 ; For compatibility
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.equ PORTD3 = 3 ;
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.equ PD3 = 3 ; For compatibility
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.equ PORTD4 = 4 ;
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.equ PD4 = 4 ; For compatibility
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.equ PORTD5 = 5 ;
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.equ PD5 = 5 ; For compatibility
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.equ PORTD6 = 6 ;
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.equ PD6 = 6 ; For compatibility
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; DDRD - Data Direction Register, Port D
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.equ DDD0 = 0 ;
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.equ DDD1 = 1 ;
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.equ DDD2 = 2 ;
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.equ DDD3 = 3 ;
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.equ DDD4 = 4 ;
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.equ DDD5 = 5 ;
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.equ DDD6 = 6 ;
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; PIND - Input Pins, Port D
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.equ PIND0 = 0 ;
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.equ PIND1 = 1 ;
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.equ PIND2 = 2 ;
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.equ PIND3 = 3 ;
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.equ PIND4 = 4 ;
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.equ PIND5 = 5 ;
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.equ PIND6 = 6 ;
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; ***** EEPROM ***********************
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; EEAR - EEPROM Read/Write Access
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.equ EEARL = EEAR ; For compatibility
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.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEPE = 1 ; EEPROM Write Enable
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.equ EEWE = EEPE ; For compatibility
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.equ EEMPE = 2 ; EEPROM Master Write Enable
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.equ EEMWE = EEMPE ; For compatibility
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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.equ EEPM0 = 4 ;
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.equ EEPM1 = 5 ;
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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; DDRA - Port A Data Direction Register
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.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA2 = 2 ; Input Pins, Port A bit 2
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; ***** USI **************************
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; USIDR - USI Data Register
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.equ USIDR0 = 0 ; USI Data Register bit 0
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.equ USIDR1 = 1 ; USI Data Register bit 1
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.equ USIDR2 = 2 ; USI Data Register bit 2
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.equ USIDR3 = 3 ; USI Data Register bit 3
|
|
.equ USIDR4 = 4 ; USI Data Register bit 4
|
|
.equ USIDR5 = 5 ; USI Data Register bit 5
|
|
.equ USIDR6 = 6 ; USI Data Register bit 6
|
|
.equ USIDR7 = 7 ; USI Data Register bit 7
|
|
|
|
; USISR - USI Status Register
|
|
.equ USICNT0 = 0 ; USI Counter Value Bit 0
|
|
.equ USICNT1 = 1 ; USI Counter Value Bit 1
|
|
.equ USICNT2 = 2 ; USI Counter Value Bit 2
|
|
.equ USICNT3 = 3 ; USI Counter Value Bit 3
|
|
.equ USIDC = 4 ; Data Output Collision
|
|
.equ USIPF = 5 ; Stop Condition Flag
|
|
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
|
|
.equ USISIF = 7 ; Start Condition Interrupt Flag
|
|
|
|
; USICR - USI Control Register
|
|
.equ USITC = 0 ; Toggle Clock Port Pin
|
|
.equ USICLK = 1 ; Clock Strobe
|
|
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
|
|
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
|
|
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
|
|
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
|
|
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
|
|
.equ USISIE = 7 ; Start Condition Interrupt Enable
|
|
|
|
|
|
; ***** EXTERNAL_INTERRUPT ***********
|
|
; GIMSK - General Interrupt Mask Register
|
|
.equ PCIE1 = 3 ;
|
|
.equ PCIE2 = 4 ;
|
|
.equ PCIE0 = 5 ;
|
|
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
|
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
|
|
|
; EIFR - Extended Interrupt Flag Register
|
|
.equ GIFR = EIFR ; For compatibility
|
|
.equ PCIF0 = 5 ;
|
|
.equ PCIF2 = 4 ;
|
|
.equ PCIF1 = 3 ;
|
|
.equ INTF0 = 6 ; External Interrupt Flag 0
|
|
.equ INTF1 = 7 ; External Interrupt Flag 1
|
|
|
|
; PCMSK2 - Pin Change Interrupt Mask Register 2
|
|
.equ PCINT11 = 0 ; Pin Change Interrupt Mask 11
|
|
.equ PCINT12 = 1 ; Pin Change Interrupt Mask 12
|
|
.equ PCINT13 = 2 ; Pin Change Interrupt Mask 13
|
|
.equ PCINT14 = 3 ; Pin Change Interrupt Mask 14
|
|
.equ PCINT15 = 4 ; Pin Change Interrupt Mask 15
|
|
.equ PCINT16 = 5 ; Pin Change Interrupt Mask 16
|
|
.equ PCINT17 = 6 ; Pin Change Interrupt Mask 17
|
|
|
|
; PCMSK1 - Pin Change Interrupt Mask Register 1
|
|
.equ PCINT8 = 0 ; Pin Change Interrupt Mask 8
|
|
.equ PCINT9 = 1 ; Pin Change Interrupt Mask 9
|
|
.equ PCINT10 = 2 ; Pin Change Interrupt Mask 10
|
|
|
|
|
|
; ***** CPU **************************
|
|
; SREG - Status Register
|
|
.equ SREG_C = 0 ; Carry Flag
|
|
.equ SREG_Z = 1 ; Zero Flag
|
|
.equ SREG_N = 2 ; Negative Flag
|
|
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
|
.equ SREG_S = 4 ; Sign Bit
|
|
.equ SREG_H = 5 ; Half Carry Flag
|
|
.equ SREG_T = 6 ; Bit Copy Storage
|
|
.equ SREG_I = 7 ; Global Interrupt Enable
|
|
|
|
; SPMCSR - Store Program Memory Control and Status register
|
|
.equ SPMEN = 0 ; Store Program Memory Enable
|
|
.equ PGERS = 1 ; Page Erase
|
|
.equ PGWRT = 2 ; Page Write
|
|
.equ RFLB = 3 ; Read Fuse and Lock Bits
|
|
.equ CTPB = 4 ; Clear Temporary Page Buffer
|
|
|
|
; MCUCR - MCU Control Register
|
|
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
|
|
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
|
|
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
|
|
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
|
.equ SM0 = 4 ; Sleep Mode Select Bit 0
|
|
.equ SM = SM0 ; For compatibility
|
|
.equ SE = 5 ; Sleep Enable
|
|
.equ SM1 = 6 ; Sleep Mode Select Bit 1
|
|
.equ PUD = 7 ; Pull-up Disable
|
|
|
|
; CLKPR - Clock Prescale Register
|
|
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
|
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
|
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
|
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
|
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
|
|
|
; MCUSR - MCU Status register
|
|
.equ PORF = 0 ; Power-On Reset Flag
|
|
.equ EXTRF = 1 ; External Reset Flag
|
|
.equ BORF = 2 ; Brown-out Reset Flag
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
|
|
|
; OSCCAL - Oscillator Calibration Register
|
|
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
|
|
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
|
|
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
|
|
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
|
|
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
|
|
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
|
|
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
|
|
|
|
; GTCCR - General Timer Counter Control Register
|
|
.equ SFIOR = GTCCR ; For compatibility
|
|
.equ PSR10 = 0 ;
|
|
|
|
; PCMSK - Pin-Change Mask register
|
|
.equ PCINT0 = 0 ; Pin-Change Interrupt 0
|
|
.equ PCINT1 = 1 ; Pin-Change Interrupt 1
|
|
.equ PCINT2 = 2 ; Pin-Change Interrupt 2
|
|
.equ PCINT3 = 3 ; Pin-Change Interrupt 3
|
|
.equ PCINT4 = 4 ; Pin-Change Interrupt 4
|
|
.equ PCINT5 = 5 ; Pin-Change Interrupt 5
|
|
.equ PCINT6 = 6 ; Pin-Change Interrupt 6
|
|
.equ PCINT7 = 7 ; Pin-Change Interrupt 7
|
|
|
|
; GPIOR2 - General Purpose I/O Register 2
|
|
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
|
|
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
|
|
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
|
|
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
|
|
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
|
|
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
|
|
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
|
|
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
|
|
|
|
; GPIOR1 - General Purpose I/O Register 1
|
|
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
|
|
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
|
|
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
|
|
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
|
|
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
|
|
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
|
|
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
|
|
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
|
|
|
|
; GPIOR0 - General Purpose I/O Register 0
|
|
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
|
|
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
|
|
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
|
|
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
|
|
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
|
|
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
|
|
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
|
|
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
|
|
|
|
; PRR - Power reduction register
|
|
.equ PRUSART = 0 ;
|
|
.equ PRUSI = 1 ;
|
|
.equ PRTIM0 = 2 ;
|
|
.equ PRTIM1 = 3 ;
|
|
|
|
; BODCR - BOD control register
|
|
.equ BPDSE = 0 ;
|
|
.equ BPDS = 1 ;
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lockbit
|
|
.equ LB2 = 1 ; Lockbit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; LOW fuse bits
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
|
.equ CKSEL2 = 2 ; Select Clock Source
|
|
.equ CKSEL3 = 3 ; Select Clock Source
|
|
.equ SUT0 = 4 ; Select start-up time
|
|
.equ SUT1 = 5 ; Select start-up time
|
|
.equ CKOUT = 6 ; Clock output
|
|
.equ CKDIV8 = 7 ; Divide clock by 8
|
|
|
|
; HIGH fuse bits
|
|
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
|
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
|
.equ WDTON = 4 ; Watchdog Timer Always On
|
|
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
|
.equ DWEN = 6 ; debugWIRE Enable
|
|
.equ RSTDISBL = 7 ; External reset disable
|
|
|
|
; EXTENDED fuse bits
|
|
.equ SELFPRGEN = 0 ; Self Programming Enable
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0x03ff ; Note: Word address
|
|
.equ IOEND = 0x003f
|
|
.equ SRAM_START = 0x0060
|
|
.equ SRAM_SIZE = 128
|
|
.equ RAMEND = 0x00df
|
|
.equ XRAMEND = 0x0000
|
|
.equ E2END = 0x007f
|
|
.equ EEPROMEND = 0x007f
|
|
.equ EEADRBITS = 7
|
|
#pragma AVRPART MEMORY PROG_FLASH 2048
|
|
#pragma AVRPART MEMORY EEPROM 128
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
|
|
|
|
|
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
.equ NRWW_START_ADDR = 0x0
|
|
.equ NRWW_STOP_ADDR = 0x3ff
|
|
.equ RWW_START_ADDR = 0x0
|
|
.equ RWW_STOP_ADDR = 0x0
|
|
.equ PAGESIZE = 16
|
|
|
|
|
|
|
|
; ***** INTERRUPT VECTORS ************************************************
|
|
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
|
.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
|
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
|
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
|
|
.equ OC1addr = 0x0004 ; For compatibility
|
|
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
|
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
|
.equ URXCaddr = 0x0007 ; USART, Rx Complete
|
|
.equ URXC0addr = 0x0007 ; For compatibility
|
|
.equ UDREaddr = 0x0008 ; USART Data Register Empty
|
|
.equ UDRE0addr = 0x0008 ; For compatibility
|
|
.equ UTXCaddr = 0x0009 ; USART, Tx Complete
|
|
.equ UTXC0addr = 0x0009 ; For compatibility
|
|
.equ ACIaddr = 0x000a ; Analog Comparator
|
|
.equ PCIBaddr = 0x000b ; Pin Change Interrupt Request B
|
|
.equ PCIaddr = 0x000b ; For compatibility
|
|
.equ OC1Baddr = 0x000c ;
|
|
.equ OC0Aaddr = 0x000d ;
|
|
.equ OC0Baddr = 0x000e ;
|
|
.equ USI_STARTaddr = 0x000f ; USI Start Condition
|
|
.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
|
.equ ERDYaddr = 0x0011 ;
|
|
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
|
|
.equ PCIAaddr = 0x0013 ; Pin Change Interrupt Request A
|
|
.equ PCIDaddr = 0x0014 ; Pin Change Interrupt Request D
|
|
|
|
.equ INT_VECTORS_SIZE = 21 ; size in words
|
|
|
|
#endif /* _TN2313ADEF_INC_ */
|
|
|
|
; ***** END OF FILE ******************************************************
|
|
|
|
; Project name: sleep-mode-example
|
|
; Description: Example of using sleep mode in power-down mode on avr microcontroller
|
|
; Source code: https://github.com/sergeyyarkov/attiny2313a_sleep-mode-example
|
|
; Device: ATtiny2313A
|
|
; Package: 20-pin-PDIP_SOIC
|
|
; Assembler: AVR macro assembler 2.2.7
|
|
; Clock frequency: 8MHz with CKDIV8
|
|
; Fuses: lfuse: 0x64, hfuse: 0x9F, efuse: 0xFF, lock:0xFF
|
|
;
|
|
; Written by Sergey Yarkov 29.05.2022
|
|
|
|
.list
|
|
|
|
.def temp_r = r16
|
|
.def wdt_counter = r10
|
|
|
|
.dseg ; Data segment
|
|
.org SRAM_START
|
|
|
|
.cseg ; Code segment
|
|
.org 0x00
|
|
|
|
000000 c01a rjmp RESET_vect ; External Pin, Power-on Reset, Brown-out Reset, and Watchdog Reset
|
|
000001 9518 reti ; External Interrupt Request 0
|
|
000002 9518 reti ; External Interrupt Request 1
|
|
000003 9518 reti ; Timer/Counter1 Capture Event
|
|
000004 9518 reti ; Timer/Counter1 Compare Match A
|
|
000005 9518 reti ; Timer/Counter1 Overflow
|
|
000006 9518 reti ; Timer/Counter0 Overflow
|
|
000007 9518 reti ; USART0, Rx Complete
|
|
000008 9518 reti ; USART0 Data Register Empty
|
|
000009 9518 reti ; USART0, Tx Complete
|
|
00000a 9518 reti ; Analog Comparator
|
|
00000b 9518 reti ; Change Interrupt Request 0
|
|
00000c 9518 reti ; Timer/Counter1 Compare Match B
|
|
00000d 9518 reti ; Timer/Counter0 Compare Match A
|
|
00000e 9518 reti ; Timer/Counter0 Compare Match B
|
|
00000f 9518 reti ; USI Start Condition
|
|
000010 9518 reti ; USI Overflow
|
|
000011 9518 reti ; EEPROM Ready
|
|
000012 c002 rjmp WDT_vect ; Watchdog Timer Overflow
|
|
000013 9518 reti ; Change Interrupt Request 1
|
|
000014 9518 reti ; Change Interrupt Request 2
|
|
|
|
WDT_vect:
|
|
000015 94a3 inc wdt_counter
|
|
000016 d01e rcall toggle_led
|
|
000017 b501 in temp_r, WDTCSR
|
|
000018 6400 ori temp_r, (1<<WDIE)
|
|
000019 bd01 out WDTCSR, temp_r
|
|
00001a 9518 reti
|
|
|
|
RESET_vect:
|
|
00001b ed0f ldi temp_r, low(RAMEND)
|
|
; setup stack pointer
|
|
00001c bf0d out SPL, temp_r
|
|
|
|
00001d d010 rcall init_ports
|
|
00001e d002 rcall init_sm
|
|
00001f d005 rcall init_wdt
|
|
|
|
; go to main loop
|
|
000020 c012 rjmp loop
|
|
|
|
; config sleep mode to power-down
|
|
init_sm:
|
|
000021 b705 in temp_r, MCUCR
|
|
000022 6100 ori temp_r, (1<<SM0)
|
|
000023 bf05 out MCUCR, temp_r
|
|
000024 9508 ret
|
|
|
|
; config watchdog to interrupt mode
|
|
init_wdt:
|
|
000025 94f8 cli
|
|
000026 95a8 wdr
|
|
|
|
000027 b501 in temp_r, WDTCSR
|
|
000028 6108 ori temp_r, (1<<WDCE) | (1<<WDE)
|
|
; allow changing the watchdog bits and enable watchdog
|
|
000029 bd01 out WDTCSR, temp_r
|
|
|
|
00002a e40e ldi temp_r, (1<<WDE) | (1<<WDIE) | (1<<WDP2) | (1<<WDP1)
|
|
; config watchdog to interrupt mode and setup prescaler 512K cycles (4 sec)
|
|
00002b bd01 out WDTCSR, temp_r
|
|
00002c 9478 sei
|
|
00002d 9508 ret
|
|
|
|
init_ports:
|
|
00002e ef0f ldi temp_r, 0xff
|
|
00002f bb0a out DDRA, temp_r
|
|
000030 2700 clr temp_r
|
|
000031 bb0b out PORTA, temp_r
|
|
000032 9508 ret
|
|
|
|
; main program loop
|
|
loop:
|
|
000033 d006 rcall wdt_sleep_check
|
|
000034 cffe rjmp loop
|
|
|
|
toggle_led:
|
|
000035 9ad8 sbi PORTA, PA0
|
|
000036 d01b rcall delay_100ms
|
|
000037 98d8 cbi PORTA, PA0
|
|
000038 d019 rcall delay_100ms
|
|
000039 9508 ret
|
|
|
|
wdt_sleep_check:
|
|
; how many seconds should elapse before entering sleep mode,
|
|
; subject to a prescaler of 128K cycles (1 sec)
|
|
.equ delay_seconds = 10
|
|
00003a 930f push r16
|
|
00003b e00a ldi r16, delay_seconds
|
|
00003c 16a0 cp wdt_counter, r16
|
|
00003d f408 brsh _mcu_sleep
|
|
00003e c008 rjmp _sleep_exit
|
|
_mcu_sleep:
|
|
00003f 24aa clr wdt_counter
|
|
000040 d008 rcall WDT_off
|
|
000041 b705 in temp_r, MCUCR
|
|
000042 6200 ori temp_r, (1<<SE)
|
|
000043 bf05 out MCUCR, temp_r
|
|
000044 910f pop r16
|
|
000045 94f8 cli
|
|
000046 9588 sleep
|
|
_sleep_exit:
|
|
000047 910f pop r16
|
|
000048 9508 ret
|
|
|
|
WDT_off:
|
|
000049 95a8 wdr
|
|
; clear WDRF in MCUSR
|
|
00004a e000 ldi temp_r, (0<<WDRF)
|
|
00004b bf04 out MCUSR, r16
|
|
; write logical one to WDCE and WDE
|
|
; keep old prescaler setting to prevent unintentional Watchdog Reset
|
|
00004c b501 in temp_r, WDTCSR
|
|
00004d 6108 ori temp_r, (1<<WDCE) | (1<<WDE)
|
|
00004e bd01 out WDTCSR, temp_r
|
|
; turn off WDT
|
|
00004f e000 ldi temp_r, (0<<WDE)
|
|
000050 bd01 out WDTCSR, temp_r
|
|
000051 9508 ret
|
|
|
|
delay_100ms: ; For 1MHz frequency
|
|
|
|
000052 e822 ldi r18, 130
|
|
000053 ed3c ldi r19, 220
|
|
_loop_d_100ms:
|
|
000054 953a dec r19
|
|
000055 f7f1 brne _loop_d_100ms
|
|
000056 952a dec r18
|
|
000057 f7e1 brne _loop_d_100ms
|
|
000058 0000 nop
|
|
|
|
000059 9508 ret
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESOURCE USE INFORMATION
|
|
------------------------
|
|
|
|
Notice:
|
|
The register and instruction counts are symbol table hit counts,
|
|
and hence implicitly used resources are not counted, eg, the
|
|
'lpm' instruction without operands implicitly uses r0 and z,
|
|
none of which are counted.
|
|
|
|
x,y,z are separate entities in the symbol table and are
|
|
counted separately from r26..r31 here.
|
|
|
|
.dseg memory usage only counts static data declared with .byte
|
|
|
|
"ATtiny2313A" register use summary:
|
|
x : 0 y : 0 z : 0 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
|
|
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 3 r11: 0 r12: 0
|
|
r13: 0 r14: 0 r15: 0 r16: 32 r17: 0 r18: 2 r19: 2 r20: 0
|
|
r21: 0 r22: 0 r23: 0 r24: 0 r25: 0 r26: 0 r27: 0 r28: 0
|
|
r29: 0 r30: 0 r31: 0
|
|
Registers used: 4 out of 35 (11.4%)
|
|
|
|
"ATtiny2313A" instruction use summary:
|
|
.lds : 0 .sts : 0 adc : 0 add : 0 adiw : 0 and : 0
|
|
andi : 0 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
|
|
brcc : 0 brcs : 0 break : 0 breq : 0 brge : 0 brhc : 0
|
|
brhs : 0 brid : 0 brie : 0 brlo : 0 brlt : 0 brmi : 0
|
|
brne : 2 brpl : 0 brsh : 1 brtc : 0 brts : 0 brvc : 0
|
|
brvs : 0 bset : 0 bst : 0 cbi : 1 cbr : 0 clc : 0
|
|
clh : 0 cli : 2 cln : 0 clr : 2 cls : 0 clt : 0
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clv : 0 clz : 0 com : 0 cp : 1 cpc : 0 cpi : 0
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cpse : 0 dec : 2 eor : 0 icall : 0 ijmp : 0 in : 5
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inc : 1 ld : 0 ldd : 0 ldi : 8 lds : 0 lpm : 0
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lsl : 0 lsr : 0 mov : 0 movw : 0 neg : 0 nop : 1
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or : 0 ori : 5 out : 11 pop : 2 push : 1 rcall : 8
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ret : 7 reti : 20 rjmp : 5 rol : 0 ror : 0 sbc : 0
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sbci : 0 sbi : 1 sbic : 0 sbis : 0 sbiw : 0 sbr : 0
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sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 1 sen : 0
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ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 1
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spm : 0 st : 0 std : 0 sts : 0 sub : 0 subi : 0
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swap : 0 tst : 0 wdr : 2
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Instructions used: 23 out of 105 (21.9%)
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"ATtiny2313A" memory use summary [bytes]:
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Segment Begin End Code Data Used Size Use%
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|
---------------------------------------------------------------
|
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[.cseg] 0x000000 0x0000b4 180 0 180 2048 8.8%
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|
[.dseg] 0x000060 0x000060 0 0 0 128 0.0%
|
|
[.eseg] 0x000000 0x000000 0 0 0 128 0.0%
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|
|
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Assembly complete, 0 errors, 0 warnings
|