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final
This commit is contained in:
commit
5a2a715a11
0
.gitignore
vendored
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0
.gitignore
vendored
Normal file
9
Makefile
Normal file
9
Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
SRC_FILE = firmware
|
||||
MCU = t2313
|
||||
PROGRAMMER = usbtiny
|
||||
|
||||
build:
|
||||
avrasm2 -fI -W+ie $(SRC_FILE).asm -l $(SRC_FILE).lss
|
||||
|
||||
flash:
|
||||
avrdude -c $(PROGRAMMER) -p $(MCU) -U flash:w:$(SRC_FILE).hex:i
|
||||
7
README.md
Normal file
7
README.md
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@ -0,0 +1,7 @@
|
||||
# Shift Register Example with USI module
|
||||
|
||||
This project is an example of using the 74HC595 shift register with the AVR ATtiny2313A microcontroller. The code in the project uses the Universal Serial Interface (USI) module on the ATtiny2313A to transmit data to the 74HC595 shift register. The transfer of data is managed using the USI Overflow Interrupt Flag, and once the transfer is completed, a pulse is sent to the LATCH pin to copy the data from the shift register to the storage register. This project demonstrates how to use the 74HC595 shift register in combination with the ATtiny2313A microcontroller to control a series of outputs.
|
||||
|
||||
|
||||
|
||||
Also see [this](https://github.com/sergeyyarkov/attiny2313a_shift-register-example) example of interaction with a shift register without a USI module
|
||||
116
firmware.asm
Normal file
116
firmware.asm
Normal file
@ -0,0 +1,116 @@
|
||||
;
|
||||
; Project name: shift-register-example
|
||||
; Description: An example of using the single 74HC595 shift register with an AVR microcontroller
|
||||
; Source code: https://github.com/sergeyyarkov/attiny2313a_shift-register-example
|
||||
; Device: ATtiny2313A
|
||||
; Device Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf
|
||||
; Package: SOIC-20W_7.5x12.8mm_P1.27mm
|
||||
; Assembler: AVR macro assembler 2.2.7
|
||||
; Clock frequency: 8 MHz Internal with CKDIV8
|
||||
; Fuses: lfuse: 0x64, hfuse: 0x9F, efuse: 0xFF, lock: 0xFF
|
||||
;
|
||||
; Written by Sergey Yarkov 28.01.2023
|
||||
|
||||
.INCLUDE "tn2313Adef.inc"
|
||||
.LIST
|
||||
|
||||
.DEF TEMP_REG_A = r16 ; Temp register A
|
||||
.DEF TEMP_REG_B = r17 ; Temp register B
|
||||
.DEF DATA = r20 ; DATA to transmit
|
||||
|
||||
;========================================;
|
||||
; LABELS ;
|
||||
;========================================;
|
||||
|
||||
.EQU USI_LATCH_PIN = PB0 ; ST_CP on 74HC595
|
||||
.EQU USI_DO_PIN = PB6 ; DS on 74HC595
|
||||
.EQU USI_CLK_PIN = PB7 ; SH_CP on 74HC595
|
||||
|
||||
;========================================;
|
||||
; CODE SEGMENT ;
|
||||
;========================================;
|
||||
|
||||
.CSEG
|
||||
.ORG 0x00
|
||||
|
||||
;========================================;
|
||||
; VECTORS ;
|
||||
;========================================;
|
||||
|
||||
rjmp RESET_vect ; Program start at RESET vector
|
||||
|
||||
RESET_vect:
|
||||
;========================================;
|
||||
; INITIALIZE STACK POINTER ;
|
||||
;========================================;
|
||||
|
||||
ldi TEMP_REG_A, low(RAMEND)
|
||||
out SPL, TEMP_REG_A
|
||||
|
||||
MCU_INIT:
|
||||
rcall INIT_PORTS
|
||||
ldi DATA, 0b00000001
|
||||
rjmp LOOP
|
||||
|
||||
;========================================;
|
||||
; MAIN PROGRAM LOOP ;
|
||||
;========================================;
|
||||
|
||||
LOOP:
|
||||
rcall USI_TRANSMIT
|
||||
rol DATA
|
||||
rcall DELAY
|
||||
rjmp LOOP
|
||||
|
||||
INIT_PORTS:
|
||||
ldi r16, (1<<USI_CLK_PIN) | (1<<USI_DO_PIN) | (1<<USI_LATCH_PIN)
|
||||
out DDRB, r16
|
||||
ret
|
||||
;========================================;
|
||||
; SEND BYTE TO 74HC595 ;
|
||||
;========================================;
|
||||
|
||||
USI_TRANSMIT:
|
||||
; Move the value stored in DATA into the R19 register
|
||||
mov r19, DATA
|
||||
out USIDR, r19
|
||||
|
||||
; Enable the USI Overflow Interrupt Flag (will be 0 if transfer is not completed)
|
||||
ldi r19, (1<<USIOIF)
|
||||
out USISR, r19
|
||||
|
||||
; Load the USI settings into a temp register to set up the USI for Three-wire mode
|
||||
; with software clock strobe (USITC) and external positive edge toggle of USCK
|
||||
;
|
||||
; USIWM0 <--------------> USI Wire Mode
|
||||
; USICS1 <--------------> USI Clock Source Select
|
||||
; USICLK <--------------> USI Clock Strobe
|
||||
; USITC <--------------> USI Toggle Clock (Enable clock generation)
|
||||
ldi TEMP_REG_A, (1<<USIWM0) | (1<<USICS1) | (1<<USICLK) | (1<<USITC)
|
||||
|
||||
_USI_TRANSMIT_LOOP: ; Execute the loop until the transfer is completed (USIOIF is 0)
|
||||
out USICR, TEMP_REG_A ; Load the settings from the temp register into the USI Control Register
|
||||
sbis USISR, USIOIF ; Check if transfer is completed and exit loop if it is
|
||||
rjmp _USI_TRANSMIT_LOOP
|
||||
|
||||
; Send a pulse to the LATCH pin to copy the byte from the 74hc595 shift register
|
||||
; to the storage register
|
||||
sbi PORTB, USI_LATCH_PIN
|
||||
cbi PORTB, USI_LATCH_PIN
|
||||
ret
|
||||
|
||||
DELAY:
|
||||
push TEMP_REG_A
|
||||
ldi TEMP_REG_A, 70
|
||||
_DELAY_1:
|
||||
ldi TEMP_REG_B, 255
|
||||
_DELAY_2:
|
||||
dec TEMP_REG_B
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
brne _DELAY_2
|
||||
dec TEMP_REG_A
|
||||
brne _DELAY_1
|
||||
pop TEMP_REG_A
|
||||
ret
|
||||
7
firmware.hex
Normal file
7
firmware.hex
Normal file
@ -0,0 +1,7 @@
|
||||
:020000020000FC
|
||||
:1000000000C00FED0DBF06D041E000C006D0441F78
|
||||
:100010000FD0FCCF01EC07BB0895342F3FB930E47B
|
||||
:100020003EB90BE10DB9769BFDCFC09AC0980895FB
|
||||
:100030000F9306E41FEF1A95000000000000D9F7A7
|
||||
:080040000A95C1F70F91089524
|
||||
:00000001FF
|
||||
872
firmware.lss
Normal file
872
firmware.lss
Normal file
@ -0,0 +1,872 @@
|
||||
|
||||
AVRASM ver. 2.2.7 firmware.asm Fri Feb 03 20:50:28 2023
|
||||
|
||||
firmware.asm(14): Including file 'tn2313Adef.inc'
|
||||
firmware.asm(14): Including file 'tn2313Adef.inc'
|
||||
|
||||
|
||||
; Project name: shift-register-example
|
||||
; Description: An example of using the single 74HC595 shift register with an AVR microcontroller
|
||||
; Source code: https://github.com/sergeyyarkov/attiny2313a_shift-register-example
|
||||
; Device: ATtiny2313A
|
||||
; Device Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/doc8246.pdf
|
||||
; Package: SOIC-20W_7.5x12.8mm_P1.27mm
|
||||
; Assembler: AVR macro assembler 2.2.7
|
||||
; Clock frequency: 8 MHz Internal with CKDIV8
|
||||
; Fuses: lfuse: 0x64, hfuse: 0x9F, efuse: 0xFF, lock: 0xFF
|
||||
;
|
||||
; Written by Sergey Yarkov 28.01.2023
|
||||
|
||||
.INCLUDE "tn2313Adef.inc"
|
||||
|
||||
;***** Created: 2011-02-09 12:04 ******* Source: ATtiny2313A.xml *********
|
||||
;*************************************************************************
|
||||
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
|
||||
;*
|
||||
;* Number : AVR000
|
||||
;* File Name : "tn2313Adef.inc"
|
||||
;* Title : Register/Bit Definitions for the ATtiny2313A
|
||||
;* Date : 2011-02-09
|
||||
;* Version : 2.35
|
||||
;* Support E-mail : avr@atmel.com
|
||||
;* Target MCU : ATtiny2313A
|
||||
;*
|
||||
;* DESCRIPTION
|
||||
;* When including this file in the assembly program file, all I/O register
|
||||
;* names and I/O register bit names appearing in the data book can be used.
|
||||
;* In addition, the six registers forming the three data pointers X, Y and
|
||||
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
|
||||
;* SRAM is also defined
|
||||
;*
|
||||
;* The Register names are represented by their hexadecimal address.
|
||||
;*
|
||||
;* The Register Bit names are represented by their bit number (0-7).
|
||||
;*
|
||||
;* Please observe the difference in using the bit names with instructions
|
||||
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
|
||||
;* (skip if bit in register set/cleared). The following example illustrates
|
||||
;* this:
|
||||
;*
|
||||
;* in r16,PORTB ;read PORTB latch
|
||||
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
|
||||
;* out PORTB,r16 ;output to PORTB
|
||||
;*
|
||||
;* in r16,TIFR ;read the Timer Interrupt Flag Register
|
||||
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
|
||||
;* rjmp TOV0_is_set ;jump if set
|
||||
;* ... ;otherwise do something else
|
||||
;*************************************************************************
|
||||
|
||||
#ifndef _TN2313ADEF_INC_
|
||||
#define _TN2313ADEF_INC_
|
||||
|
||||
|
||||
#pragma partinc 0
|
||||
|
||||
; ***** SPECIFY DEVICE ***************************************************
|
||||
.device ATtiny2313A
|
||||
#pragma AVRPART ADMIN PART_NAME ATtiny2313A
|
||||
.equ SIGNATURE_000 = 0x1e
|
||||
.equ SIGNATURE_001 = 0x91
|
||||
.equ SIGNATURE_002 = 0x0a
|
||||
|
||||
#pragma AVRPART CORE CORE_VERSION V2
|
||||
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
|
||||
|
||||
|
||||
; ***** I/O REGISTER DEFINITIONS *****************************************
|
||||
; NOTE:
|
||||
; Definitions marked "MEMORY MAPPED"are extended I/O ports
|
||||
; and cannot be used with IN/OUT instructions
|
||||
.equ SREG = 0x3f
|
||||
.equ SPL = 0x3d
|
||||
.equ OCR0B = 0x3c
|
||||
.equ GIMSK = 0x3b
|
||||
.equ EIFR = 0x3a
|
||||
.equ TIMSK = 0x39
|
||||
.equ TIFR = 0x38
|
||||
.equ SPMCSR = 0x37
|
||||
.equ OCR0A = 0x36
|
||||
.equ MCUCR = 0x35
|
||||
.equ MCUSR = 0x34
|
||||
.equ TCCR0B = 0x33
|
||||
.equ TCNT0 = 0x32
|
||||
.equ OSCCAL = 0x31
|
||||
.equ TCCR0A = 0x30
|
||||
.equ TCCR1A = 0x2f
|
||||
.equ TCCR1B = 0x2e
|
||||
.equ TCNT1L = 0x2c
|
||||
.equ TCNT1H = 0x2d
|
||||
.equ OCR1AL = 0x2a
|
||||
.equ OCR1AH = 0x2b
|
||||
.equ OCR1BL = 0x28
|
||||
.equ OCR1BH = 0x29
|
||||
.equ CLKPR = 0x26
|
||||
.equ ICR1L = 0x24
|
||||
.equ ICR1H = 0x25
|
||||
.equ GTCCR = 0x23
|
||||
.equ TCCR1C = 0x22
|
||||
.equ WDTCR = 0x21
|
||||
.equ PCMSK0 = 0x20
|
||||
.equ EEAR = 0x1e
|
||||
.equ EEDR = 0x1d
|
||||
.equ EECR = 0x1c
|
||||
.equ PORTA = 0x1b
|
||||
.equ DDRA = 0x1a
|
||||
.equ PINA = 0x19
|
||||
.equ PORTB = 0x18
|
||||
.equ DDRB = 0x17
|
||||
.equ PINB = 0x16
|
||||
.equ GPIOR2 = 0x15
|
||||
.equ GPIOR1 = 0x14
|
||||
.equ GPIOR0 = 0x13
|
||||
.equ PORTD = 0x12
|
||||
.equ DDRD = 0x11
|
||||
.equ PIND = 0x10
|
||||
.equ USIDR = 0x0f
|
||||
.equ USISR = 0x0e
|
||||
.equ USICR = 0x0d
|
||||
.equ UDR = 0x0c
|
||||
.equ UCSRA = 0x0b
|
||||
.equ UCSRB = 0x0a
|
||||
.equ UBRRL = 0x09
|
||||
.equ ACSR = 0x08
|
||||
.equ BODCR = 0x07
|
||||
.equ PRR = 0x06
|
||||
.equ PCMSK2 = 0x05
|
||||
.equ PCMSK1 = 0x04
|
||||
.equ UCSRC = 0x03
|
||||
.equ UBRRH = 0x02
|
||||
.equ DIDR = 0x01
|
||||
|
||||
|
||||
; ***** BIT DEFINITIONS **************************************************
|
||||
|
||||
; ***** PORTB ************************
|
||||
; PORTB - Port B Data Register
|
||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||||
.equ PB0 = 0 ; For compatibility
|
||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||||
.equ PB1 = 1 ; For compatibility
|
||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||||
.equ PB2 = 2 ; For compatibility
|
||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||||
.equ PB3 = 3 ; For compatibility
|
||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||||
.equ PB4 = 4 ; For compatibility
|
||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||||
.equ PB5 = 5 ; For compatibility
|
||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||||
.equ PB6 = 6 ; For compatibility
|
||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||||
.equ PB7 = 7 ; For compatibility
|
||||
|
||||
; DDRB - Port B Data Direction Register
|
||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||||
|
||||
; PINB - Port B Input Pins
|
||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_0 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||||
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
|
||||
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||||
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
|
||||
|
||||
; OCR0B - Timer/Counter0 Output Compare Register
|
||||
.equ OCR0_0 = 0 ;
|
||||
.equ OCR0_1 = 1 ;
|
||||
.equ OCR0_2 = 2 ;
|
||||
.equ OCR0_3 = 3 ;
|
||||
.equ OCR0_4 = 4 ;
|
||||
.equ OCR0_5 = 5 ;
|
||||
.equ OCR0_6 = 6 ;
|
||||
.equ OCR0_7 = 7 ;
|
||||
|
||||
; OCR0A - Timer/Counter0 Output Compare Register
|
||||
.equ OCR0A_0 = 0 ;
|
||||
.equ OCR0A_1 = 1 ;
|
||||
.equ OCR0A_2 = 2 ;
|
||||
.equ OCR0A_3 = 3 ;
|
||||
.equ OCR0A_4 = 4 ;
|
||||
.equ OCR0A_5 = 5 ;
|
||||
.equ OCR0A_6 = 6 ;
|
||||
.equ OCR0A_7 = 7 ;
|
||||
|
||||
; TCCR0A - Timer/Counter Control Register A
|
||||
.equ WGM00 = 0 ; Waveform Generation Mode
|
||||
.equ WGM01 = 1 ; Waveform Generation Mode
|
||||
.equ COM0B0 = 4 ; Compare Match Output B Mode
|
||||
.equ COM0B1 = 5 ; Compare Match Output B Mode
|
||||
.equ COM0A0 = 6 ; Compare Match Output A Mode
|
||||
.equ COM0A1 = 7 ; Compare Match Output A Mode
|
||||
|
||||
; TCNT0 - Timer/Counter0
|
||||
.equ TCNT0_0 = 0 ;
|
||||
.equ TCNT0_1 = 1 ;
|
||||
.equ TCNT0_2 = 2 ;
|
||||
.equ TCNT0_3 = 3 ;
|
||||
.equ TCNT0_4 = 4 ;
|
||||
.equ TCNT0_5 = 5 ;
|
||||
.equ TCNT0_6 = 6 ;
|
||||
.equ TCNT0_7 = 7 ;
|
||||
|
||||
; TCCR0B - Timer/Counter Control Register B
|
||||
.equ TCCR0 = TCCR0B ; For compatibility
|
||||
.equ CS00 = 0 ; Clock Select
|
||||
.equ CS01 = 1 ; Clock Select
|
||||
.equ CS02 = 2 ; Clock Select
|
||||
.equ WGM02 = 3 ;
|
||||
.equ FOC0B = 6 ; Force Output Compare B
|
||||
.equ FOC0A = 7 ; Force Output Compare B
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_1 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
||||
.equ TICIE = ICIE1 ; For compatibility
|
||||
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ ICF1 = 3 ; Input Capture Flag 1
|
||||
.equ OCF1B = 5 ; Output Compare Flag 1B
|
||||
.equ OCF1A = 6 ; Output Compare Flag 1A
|
||||
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
||||
|
||||
; TCCR1A - Timer/Counter1 Control Register A
|
||||
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
|
||||
.equ PWM10 = WGM10 ; For compatibility
|
||||
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
|
||||
.equ PWM11 = WGM11 ; For compatibility
|
||||
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
|
||||
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
||||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||||
|
||||
; TCCR1B - Timer/Counter1 Control Register B
|
||||
.equ CS10 = 0 ; Clock Select bit 0
|
||||
.equ CS11 = 1 ; Clock Select 1 bit 1
|
||||
.equ CS12 = 2 ; Clock Select1 bit 2
|
||||
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
|
||||
.equ CTC1 = WGM12 ; For compatibility
|
||||
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
|
||||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||||
|
||||
; TCCR1C - Timer/Counter1 Control Register C
|
||||
.equ FOC1B = 6 ; Force Output Compare for Channel B
|
||||
.equ FOC1A = 7 ; Force Output Compare for Channel A
|
||||
|
||||
|
||||
; ***** WATCHDOG *********************
|
||||
; WDTCR - Watchdog Timer Control Register
|
||||
.equ WDTCSR = WDTCR ; For compatibility
|
||||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||||
.equ WDE = 3 ; Watch Dog Enable
|
||||
.equ WDCE = 4 ; Watchdog Change Enable
|
||||
.equ WDTOE = WDCE ; For compatibility
|
||||
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
||||
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
||||
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
||||
|
||||
|
||||
; ***** USART ************************
|
||||
; UDR - USART I/O Data Register
|
||||
.equ UDR0 = 0 ; USART I/O Data Register bit 0
|
||||
.equ UDR1 = 1 ; USART I/O Data Register bit 1
|
||||
.equ UDR2 = 2 ; USART I/O Data Register bit 2
|
||||
.equ UDR3 = 3 ; USART I/O Data Register bit 3
|
||||
.equ UDR4 = 4 ; USART I/O Data Register bit 4
|
||||
.equ UDR5 = 5 ; USART I/O Data Register bit 5
|
||||
.equ UDR6 = 6 ; USART I/O Data Register bit 6
|
||||
.equ UDR7 = 7 ; USART I/O Data Register bit 7
|
||||
|
||||
; UCSRA - USART Control and Status Register A
|
||||
.equ USR = UCSRA ; For compatibility
|
||||
.equ MPCM = 0 ; Multi-processor Communication Mode
|
||||
.equ U2X = 1 ; Double the USART Transmission Speed
|
||||
.equ UPE = 2 ; USART Parity Error
|
||||
.equ PE = UPE ; For compatibility
|
||||
.equ DOR = 3 ; Data overRun
|
||||
.equ FE = 4 ; Framing Error
|
||||
.equ UDRE = 5 ; USART Data Register Empty
|
||||
.equ TXC = 6 ; USART Transmitt Complete
|
||||
.equ RXC = 7 ; USART Receive Complete
|
||||
|
||||
; UCSRB - USART Control and Status Register B
|
||||
.equ UCR = UCSRB ; For compatibility
|
||||
.equ TXB8 = 0 ; Transmit Data Bit 8
|
||||
.equ RXB8 = 1 ; Receive Data Bit 8
|
||||
.equ UCSZ2 = 2 ; Character Size
|
||||
.equ CHR9 = UCSZ2 ; For compatibility
|
||||
.equ TXEN = 3 ; Transmitter Enable
|
||||
.equ RXEN = 4 ; Receiver Enable
|
||||
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
|
||||
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||||
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||||
|
||||
; UCSRC - USART Control and Status Register C
|
||||
.equ UCPOL = 0 ; Clock Polarity
|
||||
.equ UCSZ0 = 1 ; Character Size Bit 0
|
||||
.equ UCSZ1 = 2 ; Character Size Bit 1
|
||||
.equ USBS = 3 ; Stop Bit Select
|
||||
.equ UPM0 = 4 ; Parity Mode Bit 0
|
||||
.equ UPM1 = 5 ; Parity Mode Bit 1
|
||||
.equ UMSEL0 = 6 ; USART Mode Select 0
|
||||
.equ UMSEL1 = 7 ; USART Mode Select 1
|
||||
.equ UCPHA = 1 ; USART MSPIM Clock Phase
|
||||
.equ UDORD = 2 ; USART MSPIM Data Order
|
||||
|
||||
.equ UBRR = UBRRL ; For compatibility
|
||||
|
||||
; ***** ANALOG_COMPARATOR ************
|
||||
; ACSR - Analog Comparator Control And Status Register
|
||||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||||
.equ ACIC = 2 ;
|
||||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||||
.equ ACO = 5 ; Analog Compare Output
|
||||
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||||
.equ ACD = 7 ; Analog Comparator Disable
|
||||
|
||||
; DIDR - Digital Input Disable Register 1
|
||||
.equ AIN0D = 0 ; AIN0 Digital Input Disable
|
||||
.equ AIN1D = 1 ; AIN1 Digital Input Disable
|
||||
|
||||
|
||||
; ***** PORTD ************************
|
||||
; PORTD - Data Register, Port D
|
||||
.equ PORTD0 = 0 ;
|
||||
.equ PD0 = 0 ; For compatibility
|
||||
.equ PORTD1 = 1 ;
|
||||
.equ PD1 = 1 ; For compatibility
|
||||
.equ PORTD2 = 2 ;
|
||||
.equ PD2 = 2 ; For compatibility
|
||||
.equ PORTD3 = 3 ;
|
||||
.equ PD3 = 3 ; For compatibility
|
||||
.equ PORTD4 = 4 ;
|
||||
.equ PD4 = 4 ; For compatibility
|
||||
.equ PORTD5 = 5 ;
|
||||
.equ PD5 = 5 ; For compatibility
|
||||
.equ PORTD6 = 6 ;
|
||||
.equ PD6 = 6 ; For compatibility
|
||||
|
||||
; DDRD - Data Direction Register, Port D
|
||||
.equ DDD0 = 0 ;
|
||||
.equ DDD1 = 1 ;
|
||||
.equ DDD2 = 2 ;
|
||||
.equ DDD3 = 3 ;
|
||||
.equ DDD4 = 4 ;
|
||||
.equ DDD5 = 5 ;
|
||||
.equ DDD6 = 6 ;
|
||||
|
||||
; PIND - Input Pins, Port D
|
||||
.equ PIND0 = 0 ;
|
||||
.equ PIND1 = 1 ;
|
||||
.equ PIND2 = 2 ;
|
||||
.equ PIND3 = 3 ;
|
||||
.equ PIND4 = 4 ;
|
||||
.equ PIND5 = 5 ;
|
||||
.equ PIND6 = 6 ;
|
||||
|
||||
|
||||
; ***** EEPROM ***********************
|
||||
; EEAR - EEPROM Read/Write Access
|
||||
.equ EEARL = EEAR ; For compatibility
|
||||
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
|
||||
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
|
||||
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
|
||||
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
|
||||
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
|
||||
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
|
||||
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
|
||||
|
||||
; EEDR - EEPROM Data Register
|
||||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||||
|
||||
; EECR - EEPROM Control Register
|
||||
.equ EERE = 0 ; EEPROM Read Enable
|
||||
.equ EEPE = 1 ; EEPROM Write Enable
|
||||
.equ EEWE = EEPE ; For compatibility
|
||||
.equ EEMPE = 2 ; EEPROM Master Write Enable
|
||||
.equ EEMWE = EEMPE ; For compatibility
|
||||
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
|
||||
.equ EEPM0 = 4 ;
|
||||
.equ EEPM1 = 5 ;
|
||||
|
||||
|
||||
; ***** PORTA ************************
|
||||
; PORTA - Port A Data Register
|
||||
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
||||
.equ PA0 = 0 ; For compatibility
|
||||
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
||||
.equ PA1 = 1 ; For compatibility
|
||||
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
||||
.equ PA2 = 2 ; For compatibility
|
||||
|
||||
; DDRA - Port A Data Direction Register
|
||||
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
||||
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
||||
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
||||
|
||||
; PINA - Port A Input Pins
|
||||
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
||||
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
||||
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
||||
|
||||
|
||||
; ***** USI **************************
|
||||
; USIDR - USI Data Register
|
||||
.equ USIDR0 = 0 ; USI Data Register bit 0
|
||||
.equ USIDR1 = 1 ; USI Data Register bit 1
|
||||
.equ USIDR2 = 2 ; USI Data Register bit 2
|
||||
.equ USIDR3 = 3 ; USI Data Register bit 3
|
||||
.equ USIDR4 = 4 ; USI Data Register bit 4
|
||||
.equ USIDR5 = 5 ; USI Data Register bit 5
|
||||
.equ USIDR6 = 6 ; USI Data Register bit 6
|
||||
.equ USIDR7 = 7 ; USI Data Register bit 7
|
||||
|
||||
; USISR - USI Status Register
|
||||
.equ USICNT0 = 0 ; USI Counter Value Bit 0
|
||||
.equ USICNT1 = 1 ; USI Counter Value Bit 1
|
||||
.equ USICNT2 = 2 ; USI Counter Value Bit 2
|
||||
.equ USICNT3 = 3 ; USI Counter Value Bit 3
|
||||
.equ USIDC = 4 ; Data Output Collision
|
||||
.equ USIPF = 5 ; Stop Condition Flag
|
||||
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
|
||||
.equ USISIF = 7 ; Start Condition Interrupt Flag
|
||||
|
||||
; USICR - USI Control Register
|
||||
.equ USITC = 0 ; Toggle Clock Port Pin
|
||||
.equ USICLK = 1 ; Clock Strobe
|
||||
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
|
||||
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
|
||||
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
|
||||
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
|
||||
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
|
||||
.equ USISIE = 7 ; Start Condition Interrupt Enable
|
||||
|
||||
|
||||
; ***** EXTERNAL_INTERRUPT ***********
|
||||
; GIMSK - General Interrupt Mask Register
|
||||
.equ PCIE1 = 3 ;
|
||||
.equ PCIE2 = 4 ;
|
||||
.equ PCIE0 = 5 ;
|
||||
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||||
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
||||
|
||||
; EIFR - Extended Interrupt Flag Register
|
||||
.equ GIFR = EIFR ; For compatibility
|
||||
.equ PCIF0 = 5 ;
|
||||
.equ PCIF2 = 4 ;
|
||||
.equ PCIF1 = 3 ;
|
||||
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||||
.equ INTF1 = 7 ; External Interrupt Flag 1
|
||||
|
||||
; PCMSK2 - Pin Change Interrupt Mask Register 2
|
||||
.equ PCINT11 = 0 ; Pin Change Interrupt Mask 11
|
||||
.equ PCINT12 = 1 ; Pin Change Interrupt Mask 12
|
||||
.equ PCINT13 = 2 ; Pin Change Interrupt Mask 13
|
||||
.equ PCINT14 = 3 ; Pin Change Interrupt Mask 14
|
||||
.equ PCINT15 = 4 ; Pin Change Interrupt Mask 15
|
||||
.equ PCINT16 = 5 ; Pin Change Interrupt Mask 16
|
||||
.equ PCINT17 = 6 ; Pin Change Interrupt Mask 17
|
||||
|
||||
; PCMSK1 - Pin Change Interrupt Mask Register 1
|
||||
.equ PCINT8 = 0 ; Pin Change Interrupt Mask 8
|
||||
.equ PCINT9 = 1 ; Pin Change Interrupt Mask 9
|
||||
.equ PCINT10 = 2 ; Pin Change Interrupt Mask 10
|
||||
|
||||
|
||||
; ***** CPU **************************
|
||||
; SREG - Status Register
|
||||
.equ SREG_C = 0 ; Carry Flag
|
||||
.equ SREG_Z = 1 ; Zero Flag
|
||||
.equ SREG_N = 2 ; Negative Flag
|
||||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||||
.equ SREG_S = 4 ; Sign Bit
|
||||
.equ SREG_H = 5 ; Half Carry Flag
|
||||
.equ SREG_T = 6 ; Bit Copy Storage
|
||||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||||
|
||||
; SPMCSR - Store Program Memory Control and Status register
|
||||
.equ SPMEN = 0 ; Store Program Memory Enable
|
||||
.equ PGERS = 1 ; Page Erase
|
||||
.equ PGWRT = 2 ; Page Write
|
||||
.equ RFLB = 3 ; Read Fuse and Lock Bits
|
||||
.equ CTPB = 4 ; Clear Temporary Page Buffer
|
||||
|
||||
; MCUCR - MCU Control Register
|
||||
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
|
||||
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
|
||||
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
|
||||
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
||||
.equ SM0 = 4 ; Sleep Mode Select Bit 0
|
||||
.equ SM = SM0 ; For compatibility
|
||||
.equ SE = 5 ; Sleep Enable
|
||||
.equ SM1 = 6 ; Sleep Mode Select Bit 1
|
||||
.equ PUD = 7 ; Pull-up Disable
|
||||
|
||||
; CLKPR - Clock Prescale Register
|
||||
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
||||
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
||||
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
||||
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
||||
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
||||
|
||||
; MCUSR - MCU Status register
|
||||
.equ PORF = 0 ; Power-On Reset Flag
|
||||
.equ EXTRF = 1 ; External Reset Flag
|
||||
.equ BORF = 2 ; Brown-out Reset Flag
|
||||
.equ WDRF = 3 ; Watchdog Reset Flag
|
||||
|
||||
; OSCCAL - Oscillator Calibration Register
|
||||
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
|
||||
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
|
||||
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
|
||||
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
|
||||
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
|
||||
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
|
||||
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
|
||||
|
||||
; GTCCR - General Timer Counter Control Register
|
||||
.equ SFIOR = GTCCR ; For compatibility
|
||||
.equ PSR10 = 0 ;
|
||||
|
||||
; PCMSK - Pin-Change Mask register
|
||||
.equ PCINT0 = 0 ; Pin-Change Interrupt 0
|
||||
.equ PCINT1 = 1 ; Pin-Change Interrupt 1
|
||||
.equ PCINT2 = 2 ; Pin-Change Interrupt 2
|
||||
.equ PCINT3 = 3 ; Pin-Change Interrupt 3
|
||||
.equ PCINT4 = 4 ; Pin-Change Interrupt 4
|
||||
.equ PCINT5 = 5 ; Pin-Change Interrupt 5
|
||||
.equ PCINT6 = 6 ; Pin-Change Interrupt 6
|
||||
.equ PCINT7 = 7 ; Pin-Change Interrupt 7
|
||||
|
||||
; GPIOR2 - General Purpose I/O Register 2
|
||||
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
|
||||
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
|
||||
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
|
||||
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
|
||||
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
|
||||
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
|
||||
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
|
||||
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
|
||||
|
||||
; GPIOR1 - General Purpose I/O Register 1
|
||||
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
|
||||
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
|
||||
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
|
||||
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
|
||||
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
|
||||
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
|
||||
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
|
||||
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
|
||||
|
||||
; GPIOR0 - General Purpose I/O Register 0
|
||||
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
|
||||
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
|
||||
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
|
||||
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
|
||||
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
|
||||
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
|
||||
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
|
||||
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
|
||||
|
||||
; PRR - Power reduction register
|
||||
.equ PRUSART = 0 ;
|
||||
.equ PRUSI = 1 ;
|
||||
.equ PRTIM0 = 2 ;
|
||||
.equ PRTIM1 = 3 ;
|
||||
|
||||
; BODCR - BOD control register
|
||||
.equ BPDSE = 0 ;
|
||||
.equ BPDS = 1 ;
|
||||
|
||||
|
||||
|
||||
; ***** LOCKSBITS ********************************************************
|
||||
.equ LB1 = 0 ; Lockbit
|
||||
.equ LB2 = 1 ; Lockbit
|
||||
|
||||
|
||||
; ***** FUSES ************************************************************
|
||||
; LOW fuse bits
|
||||
.equ CKSEL0 = 0 ; Select Clock Source
|
||||
.equ CKSEL1 = 1 ; Select Clock Source
|
||||
.equ CKSEL2 = 2 ; Select Clock Source
|
||||
.equ CKSEL3 = 3 ; Select Clock Source
|
||||
.equ SUT0 = 4 ; Select start-up time
|
||||
.equ SUT1 = 5 ; Select start-up time
|
||||
.equ CKOUT = 6 ; Clock output
|
||||
.equ CKDIV8 = 7 ; Divide clock by 8
|
||||
|
||||
; HIGH fuse bits
|
||||
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
||||
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||||
.equ WDTON = 4 ; Watchdog Timer Always On
|
||||
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||||
.equ DWEN = 6 ; debugWIRE Enable
|
||||
.equ RSTDISBL = 7 ; External reset disable
|
||||
|
||||
; EXTENDED fuse bits
|
||||
.equ SELFPRGEN = 0 ; Self Programming Enable
|
||||
|
||||
|
||||
|
||||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||||
.def XH = r27
|
||||
.def XL = r26
|
||||
.def YH = r29
|
||||
.def YL = r28
|
||||
.def ZH = r31
|
||||
.def ZL = r30
|
||||
|
||||
|
||||
|
||||
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||||
.equ FLASHEND = 0x03ff ; Note: Word address
|
||||
.equ IOEND = 0x003f
|
||||
.equ SRAM_START = 0x0060
|
||||
.equ SRAM_SIZE = 128
|
||||
.equ RAMEND = 0x00df
|
||||
.equ XRAMEND = 0x0000
|
||||
.equ E2END = 0x007f
|
||||
.equ EEPROMEND = 0x007f
|
||||
.equ EEADRBITS = 7
|
||||
#pragma AVRPART MEMORY PROG_FLASH 2048
|
||||
#pragma AVRPART MEMORY EEPROM 128
|
||||
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||||
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||||
|
||||
|
||||
|
||||
; ***** BOOTLOADER DECLARATIONS ******************************************
|
||||
.equ NRWW_START_ADDR = 0x0
|
||||
.equ NRWW_STOP_ADDR = 0x3ff
|
||||
.equ RWW_START_ADDR = 0x0
|
||||
.equ RWW_STOP_ADDR = 0x0
|
||||
.equ PAGESIZE = 16
|
||||
|
||||
|
||||
|
||||
; ***** INTERRUPT VECTORS ************************************************
|
||||
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
||||
.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
||||
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
||||
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
|
||||
.equ OC1addr = 0x0004 ; For compatibility
|
||||
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||||
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||||
.equ URXCaddr = 0x0007 ; USART, Rx Complete
|
||||
.equ URXC0addr = 0x0007 ; For compatibility
|
||||
.equ UDREaddr = 0x0008 ; USART Data Register Empty
|
||||
.equ UDRE0addr = 0x0008 ; For compatibility
|
||||
.equ UTXCaddr = 0x0009 ; USART, Tx Complete
|
||||
.equ UTXC0addr = 0x0009 ; For compatibility
|
||||
.equ ACIaddr = 0x000a ; Analog Comparator
|
||||
.equ PCIBaddr = 0x000b ; Pin Change Interrupt Request B
|
||||
.equ PCIaddr = 0x000b ; For compatibility
|
||||
.equ OC1Baddr = 0x000c ;
|
||||
.equ OC0Aaddr = 0x000d ;
|
||||
.equ OC0Baddr = 0x000e ;
|
||||
.equ USI_STARTaddr = 0x000f ; USI Start Condition
|
||||
.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
||||
.equ ERDYaddr = 0x0011 ;
|
||||
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
|
||||
.equ PCIAaddr = 0x0013 ; Pin Change Interrupt Request A
|
||||
.equ PCIDaddr = 0x0014 ; Pin Change Interrupt Request D
|
||||
|
||||
.equ INT_VECTORS_SIZE = 21 ; size in words
|
||||
|
||||
#endif /* _TN2313ADEF_INC_ */
|
||||
|
||||
; ***** END OF FILE ******************************************************
|
||||
.LIST
|
||||
|
||||
.DEF TEMP_REG_A = r16 ; Temp register A
|
||||
.DEF TEMP_REG_B = r17 ; Temp register B
|
||||
.DEF DATA = r20 ; DATA to transmit
|
||||
|
||||
;========================================;
|
||||
; LABELS ;
|
||||
;========================================;
|
||||
|
||||
.EQU USI_LATCH_PIN = PB0 ; ST_CP on 74HC595
|
||||
.EQU USI_DO_PIN = PB6 ; DS on 74HC595
|
||||
.EQU USI_CLK_PIN = PB7 ; SH_CP on 74HC595
|
||||
|
||||
;========================================;
|
||||
; CODE SEGMENT ;
|
||||
;========================================;
|
||||
|
||||
.CSEG
|
||||
.ORG 0x00
|
||||
|
||||
;========================================;
|
||||
; VECTORS ;
|
||||
;========================================;
|
||||
|
||||
000000 c000 rjmp RESET_vect ; Program start at RESET vector
|
||||
|
||||
RESET_vect:
|
||||
;========================================;
|
||||
; INITIALIZE STACK POINTER ;
|
||||
;========================================;
|
||||
|
||||
000001 ed0f ldi TEMP_REG_A, low(RAMEND)
|
||||
000002 bf0d out SPL, TEMP_REG_A
|
||||
|
||||
MCU_INIT:
|
||||
000003 d006 rcall INIT_PORTS
|
||||
000004 e041 ldi DATA, 0b00000001
|
||||
000005 c000 rjmp LOOP
|
||||
|
||||
;========================================;
|
||||
; MAIN PROGRAM LOOP ;
|
||||
;========================================;
|
||||
|
||||
LOOP:
|
||||
000006 d006 rcall USI_TRANSMIT
|
||||
000007 1f44 rol DATA
|
||||
000008 d00f rcall DELAY
|
||||
000009 cffc rjmp LOOP
|
||||
|
||||
INIT_PORTS:
|
||||
00000a ec01 ldi r16, (1<<USI_CLK_PIN) | (1<<USI_DO_PIN) | (1<<USI_LATCH_PIN)
|
||||
00000b bb07 out DDRB, r16
|
||||
00000c 9508 ret
|
||||
;========================================;
|
||||
; SEND BYTE TO 74HC595 ;
|
||||
;========================================;
|
||||
|
||||
USI_TRANSMIT:
|
||||
; Move the value stored in DATA into the R19 register
|
||||
00000d 2f34 mov r19, DATA
|
||||
00000e b93f out USIDR, r19
|
||||
|
||||
; Enable the USI Overflow Interrupt Flag (will be 0 if transfer is not completed)
|
||||
00000f e430 ldi r19, (1<<USIOIF)
|
||||
000010 b93e out USISR, r19
|
||||
|
||||
; Load the USI settings into a temp register to set up the USI for Three-wire mode
|
||||
; with software clock strobe (USITC) and external positive edge toggle of USCK
|
||||
;
|
||||
; USIWM0 <--------------> USI Wire Mode
|
||||
; USICS1 <--------------> USI Clock Source Select
|
||||
; USICLK <--------------> USI Clock Strobe
|
||||
; USITC <--------------> USI Toggle Clock (Enable clock generation)
|
||||
000011 e10b ldi TEMP_REG_A, (1<<USIWM0) | (1<<USICS1) | (1<<USICLK) | (1<<USITC)
|
||||
|
||||
_USI_TRANSMIT_LOOP: ; Execute the loop until the transfer is completed (USIOIF is 0)
|
||||
000012 b90d out USICR, TEMP_REG_A ; Load the settings from the temp register into the USI Control Register
|
||||
000013 9b76 sbis USISR, USIOIF ; Check if transfer is completed and exit loop if it is
|
||||
000014 cffd rjmp _USI_TRANSMIT_LOOP
|
||||
|
||||
; Send a pulse to the LATCH pin to copy the byte from the 74hc595 shift register
|
||||
; to the storage register
|
||||
000015 9ac0 sbi PORTB, USI_LATCH_PIN
|
||||
000016 98c0 cbi PORTB, USI_LATCH_PIN
|
||||
000017 9508 ret
|
||||
|
||||
DELAY:
|
||||
000018 930f push TEMP_REG_A
|
||||
000019 e406 ldi TEMP_REG_A, 70
|
||||
_DELAY_1:
|
||||
00001a ef1f ldi TEMP_REG_B, 255
|
||||
_DELAY_2:
|
||||
00001b 951a dec TEMP_REG_B
|
||||
00001c 0000 nop
|
||||
00001d 0000 nop
|
||||
00001e 0000 nop
|
||||
00001f f7d9 brne _DELAY_2
|
||||
000020 950a dec TEMP_REG_A
|
||||
000021 f7c1 brne _DELAY_1
|
||||
000022 910f pop TEMP_REG_A
|
||||
|
||||
|
||||
RESOURCE USE INFORMATION
|
||||
------------------------
|
||||
|
||||
Notice:
|
||||
The register and instruction counts are symbol table hit counts,
|
||||
and hence implicitly used resources are not counted, eg, the
|
||||
'lpm' instruction without operands implicitly uses r0 and z,
|
||||
none of which are counted.
|
||||
|
||||
x,y,z are separate entities in the symbol table and are
|
||||
counted separately from r26..r31 here.
|
||||
|
||||
.dseg memory usage only counts static data declared with .byte
|
||||
|
||||
"ATtiny2313A" register use summary:
|
||||
x : 0 y : 0 z : 0 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
|
||||
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 0 r11: 0 r12: 0
|
||||
r13: 0 r14: 0 r15: 0 r16: 10 r17: 2 r18: 0 r19: 4 r20: 3
|
||||
r21: 0 r22: 0 r23: 0 r24: 0 r25: 0 r26: 0 r27: 0 r28: 0
|
||||
r29: 0 r30: 0 r31: 0
|
||||
Registers used: 4 out of 35 (11.4%)
|
||||
|
||||
"ATtiny2313A" instruction use summary:
|
||||
.lds : 0 .sts : 0 adc : 0 add : 0 adiw : 0 and : 0
|
||||
andi : 0 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
|
||||
brcc : 0 brcs : 0 break : 0 breq : 0 brge : 0 brhc : 0
|
||||
brhs : 0 brid : 0 brie : 0 brlo : 0 brlt : 0 brmi : 0
|
||||
brne : 2 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
|
||||
brvs : 0 bset : 0 bst : 0 cbi : 1 cbr : 0 clc : 0
|
||||
clh : 0 cli : 0 cln : 0 clr : 0 cls : 0 clt : 0
|
||||
clv : 0 clz : 0 com : 0 cp : 0 cpc : 0 cpi : 0
|
||||
cpse : 0 dec : 2 eor : 0 icall : 0 ijmp : 0 in : 0
|
||||
inc : 0 ld : 0 ldd : 0 ldi : 7 lds : 0 lpm : 0
|
||||
lsl : 0 lsr : 0 mov : 1 movw : 0 neg : 0 nop : 3
|
||||
or : 0 ori : 0 out : 5 pop : 1 push : 1 rcall : 3
|
||||
ret : 3 reti : 0 rjmp : 4 rol : 1 ror : 0 sbc : 0
|
||||
sbci : 0 sbi : 1 sbic : 0 sbis : 1 sbiw : 0 sbr : 0
|
||||
sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 0 sen : 0
|
||||
ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 0
|
||||
spm : 0 st : 0 std : 0 sts : 0 sub : 0 subi : 0
|
||||
swap : 0 tst : 0 wdr : 0
|
||||
Instructions used: 15 out of 105 (14.3%)
|
||||
|
||||
"ATtiny2313A" memory use summary [bytes]:
|
||||
Segment Begin End Code Data Used Size Use%
|
||||
---------------------------------------------------------------
|
||||
[.cseg] 0x000000 0x000048 72 0 72 2048 3.5%
|
||||
[.dseg] 0x000060 0x000060 0 0 0 128 0.0%
|
||||
[.eseg] 0x000000 0x000000 0 0 0 128 0.0%
|
||||
|
||||
Assembly complete, 0 errors, 0 warnings
|
||||
BIN
simulation.gif
Normal file
BIN
simulation.gif
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 886 KiB |
698
tn2313Adef.inc
Normal file
698
tn2313Adef.inc
Normal file
@ -0,0 +1,698 @@
|
||||
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
|
||||
;***** Created: 2011-02-09 12:04 ******* Source: ATtiny2313A.xml *********
|
||||
;*************************************************************************
|
||||
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
|
||||
;*
|
||||
;* Number : AVR000
|
||||
;* File Name : "tn2313Adef.inc"
|
||||
;* Title : Register/Bit Definitions for the ATtiny2313A
|
||||
;* Date : 2011-02-09
|
||||
;* Version : 2.35
|
||||
;* Support E-mail : avr@atmel.com
|
||||
;* Target MCU : ATtiny2313A
|
||||
;*
|
||||
;* DESCRIPTION
|
||||
;* When including this file in the assembly program file, all I/O register
|
||||
;* names and I/O register bit names appearing in the data book can be used.
|
||||
;* In addition, the six registers forming the three data pointers X, Y and
|
||||
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
|
||||
;* SRAM is also defined
|
||||
;*
|
||||
;* The Register names are represented by their hexadecimal address.
|
||||
;*
|
||||
;* The Register Bit names are represented by their bit number (0-7).
|
||||
;*
|
||||
;* Please observe the difference in using the bit names with instructions
|
||||
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
|
||||
;* (skip if bit in register set/cleared). The following example illustrates
|
||||
;* this:
|
||||
;*
|
||||
;* in r16,PORTB ;read PORTB latch
|
||||
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
|
||||
;* out PORTB,r16 ;output to PORTB
|
||||
;*
|
||||
;* in r16,TIFR ;read the Timer Interrupt Flag Register
|
||||
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
|
||||
;* rjmp TOV0_is_set ;jump if set
|
||||
;* ... ;otherwise do something else
|
||||
;*************************************************************************
|
||||
|
||||
#ifndef _TN2313ADEF_INC_
|
||||
#define _TN2313ADEF_INC_
|
||||
|
||||
|
||||
#pragma partinc 0
|
||||
|
||||
; ***** SPECIFY DEVICE ***************************************************
|
||||
.device ATtiny2313A
|
||||
#pragma AVRPART ADMIN PART_NAME ATtiny2313A
|
||||
.equ SIGNATURE_000 = 0x1e
|
||||
.equ SIGNATURE_001 = 0x91
|
||||
.equ SIGNATURE_002 = 0x0a
|
||||
|
||||
#pragma AVRPART CORE CORE_VERSION V2
|
||||
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
|
||||
|
||||
|
||||
; ***** I/O REGISTER DEFINITIONS *****************************************
|
||||
; NOTE:
|
||||
; Definitions marked "MEMORY MAPPED"are extended I/O ports
|
||||
; and cannot be used with IN/OUT instructions
|
||||
.equ SREG = 0x3f
|
||||
.equ SPL = 0x3d
|
||||
.equ OCR0B = 0x3c
|
||||
.equ GIMSK = 0x3b
|
||||
.equ EIFR = 0x3a
|
||||
.equ TIMSK = 0x39
|
||||
.equ TIFR = 0x38
|
||||
.equ SPMCSR = 0x37
|
||||
.equ OCR0A = 0x36
|
||||
.equ MCUCR = 0x35
|
||||
.equ MCUSR = 0x34
|
||||
.equ TCCR0B = 0x33
|
||||
.equ TCNT0 = 0x32
|
||||
.equ OSCCAL = 0x31
|
||||
.equ TCCR0A = 0x30
|
||||
.equ TCCR1A = 0x2f
|
||||
.equ TCCR1B = 0x2e
|
||||
.equ TCNT1L = 0x2c
|
||||
.equ TCNT1H = 0x2d
|
||||
.equ OCR1AL = 0x2a
|
||||
.equ OCR1AH = 0x2b
|
||||
.equ OCR1BL = 0x28
|
||||
.equ OCR1BH = 0x29
|
||||
.equ CLKPR = 0x26
|
||||
.equ ICR1L = 0x24
|
||||
.equ ICR1H = 0x25
|
||||
.equ GTCCR = 0x23
|
||||
.equ TCCR1C = 0x22
|
||||
.equ WDTCR = 0x21
|
||||
.equ PCMSK0 = 0x20
|
||||
.equ EEAR = 0x1e
|
||||
.equ EEDR = 0x1d
|
||||
.equ EECR = 0x1c
|
||||
.equ PORTA = 0x1b
|
||||
.equ DDRA = 0x1a
|
||||
.equ PINA = 0x19
|
||||
.equ PORTB = 0x18
|
||||
.equ DDRB = 0x17
|
||||
.equ PINB = 0x16
|
||||
.equ GPIOR2 = 0x15
|
||||
.equ GPIOR1 = 0x14
|
||||
.equ GPIOR0 = 0x13
|
||||
.equ PORTD = 0x12
|
||||
.equ DDRD = 0x11
|
||||
.equ PIND = 0x10
|
||||
.equ USIDR = 0x0f
|
||||
.equ USISR = 0x0e
|
||||
.equ USICR = 0x0d
|
||||
.equ UDR = 0x0c
|
||||
.equ UCSRA = 0x0b
|
||||
.equ UCSRB = 0x0a
|
||||
.equ UBRRL = 0x09
|
||||
.equ ACSR = 0x08
|
||||
.equ BODCR = 0x07
|
||||
.equ PRR = 0x06
|
||||
.equ PCMSK2 = 0x05
|
||||
.equ PCMSK1 = 0x04
|
||||
.equ UCSRC = 0x03
|
||||
.equ UBRRH = 0x02
|
||||
.equ DIDR = 0x01
|
||||
|
||||
|
||||
; ***** BIT DEFINITIONS **************************************************
|
||||
|
||||
; ***** PORTB ************************
|
||||
; PORTB - Port B Data Register
|
||||
.equ PORTB0 = 0 ; Port B Data Register bit 0
|
||||
.equ PB0 = 0 ; For compatibility
|
||||
.equ PORTB1 = 1 ; Port B Data Register bit 1
|
||||
.equ PB1 = 1 ; For compatibility
|
||||
.equ PORTB2 = 2 ; Port B Data Register bit 2
|
||||
.equ PB2 = 2 ; For compatibility
|
||||
.equ PORTB3 = 3 ; Port B Data Register bit 3
|
||||
.equ PB3 = 3 ; For compatibility
|
||||
.equ PORTB4 = 4 ; Port B Data Register bit 4
|
||||
.equ PB4 = 4 ; For compatibility
|
||||
.equ PORTB5 = 5 ; Port B Data Register bit 5
|
||||
.equ PB5 = 5 ; For compatibility
|
||||
.equ PORTB6 = 6 ; Port B Data Register bit 6
|
||||
.equ PB6 = 6 ; For compatibility
|
||||
.equ PORTB7 = 7 ; Port B Data Register bit 7
|
||||
.equ PB7 = 7 ; For compatibility
|
||||
|
||||
; DDRB - Port B Data Direction Register
|
||||
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
|
||||
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
|
||||
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
|
||||
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
|
||||
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
|
||||
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
|
||||
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
|
||||
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
|
||||
|
||||
; PINB - Port B Input Pins
|
||||
.equ PINB0 = 0 ; Port B Input Pins bit 0
|
||||
.equ PINB1 = 1 ; Port B Input Pins bit 1
|
||||
.equ PINB2 = 2 ; Port B Input Pins bit 2
|
||||
.equ PINB3 = 3 ; Port B Input Pins bit 3
|
||||
.equ PINB4 = 4 ; Port B Input Pins bit 4
|
||||
.equ PINB5 = 5 ; Port B Input Pins bit 5
|
||||
.equ PINB6 = 6 ; Port B Input Pins bit 6
|
||||
.equ PINB7 = 7 ; Port B Input Pins bit 7
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_0 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable
|
||||
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
|
||||
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A
|
||||
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
|
||||
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
|
||||
|
||||
; OCR0B - Timer/Counter0 Output Compare Register
|
||||
.equ OCR0_0 = 0 ;
|
||||
.equ OCR0_1 = 1 ;
|
||||
.equ OCR0_2 = 2 ;
|
||||
.equ OCR0_3 = 3 ;
|
||||
.equ OCR0_4 = 4 ;
|
||||
.equ OCR0_5 = 5 ;
|
||||
.equ OCR0_6 = 6 ;
|
||||
.equ OCR0_7 = 7 ;
|
||||
|
||||
; OCR0A - Timer/Counter0 Output Compare Register
|
||||
.equ OCR0A_0 = 0 ;
|
||||
.equ OCR0A_1 = 1 ;
|
||||
.equ OCR0A_2 = 2 ;
|
||||
.equ OCR0A_3 = 3 ;
|
||||
.equ OCR0A_4 = 4 ;
|
||||
.equ OCR0A_5 = 5 ;
|
||||
.equ OCR0A_6 = 6 ;
|
||||
.equ OCR0A_7 = 7 ;
|
||||
|
||||
; TCCR0A - Timer/Counter Control Register A
|
||||
.equ WGM00 = 0 ; Waveform Generation Mode
|
||||
.equ WGM01 = 1 ; Waveform Generation Mode
|
||||
.equ COM0B0 = 4 ; Compare Match Output B Mode
|
||||
.equ COM0B1 = 5 ; Compare Match Output B Mode
|
||||
.equ COM0A0 = 6 ; Compare Match Output A Mode
|
||||
.equ COM0A1 = 7 ; Compare Match Output A Mode
|
||||
|
||||
; TCNT0 - Timer/Counter0
|
||||
.equ TCNT0_0 = 0 ;
|
||||
.equ TCNT0_1 = 1 ;
|
||||
.equ TCNT0_2 = 2 ;
|
||||
.equ TCNT0_3 = 3 ;
|
||||
.equ TCNT0_4 = 4 ;
|
||||
.equ TCNT0_5 = 5 ;
|
||||
.equ TCNT0_6 = 6 ;
|
||||
.equ TCNT0_7 = 7 ;
|
||||
|
||||
; TCCR0B - Timer/Counter Control Register B
|
||||
.equ TCCR0 = TCCR0B ; For compatibility
|
||||
.equ CS00 = 0 ; Clock Select
|
||||
.equ CS01 = 1 ; Clock Select
|
||||
.equ CS02 = 2 ; Clock Select
|
||||
.equ WGM02 = 3 ;
|
||||
.equ FOC0B = 6 ; Force Output Compare B
|
||||
.equ FOC0A = 7 ; Force Output Compare B
|
||||
|
||||
|
||||
; ***** TIMER_COUNTER_1 **************
|
||||
; TIMSK - Timer/Counter Interrupt Mask Register
|
||||
.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable
|
||||
.equ TICIE = ICIE1 ; For compatibility
|
||||
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable
|
||||
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable
|
||||
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable
|
||||
|
||||
; TIFR - Timer/Counter Interrupt Flag register
|
||||
.equ ICF1 = 3 ; Input Capture Flag 1
|
||||
.equ OCF1B = 5 ; Output Compare Flag 1B
|
||||
.equ OCF1A = 6 ; Output Compare Flag 1A
|
||||
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag
|
||||
|
||||
; TCCR1A - Timer/Counter1 Control Register A
|
||||
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
|
||||
.equ PWM10 = WGM10 ; For compatibility
|
||||
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
|
||||
.equ PWM11 = WGM11 ; For compatibility
|
||||
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
|
||||
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
||||
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
||||
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
||||
|
||||
; TCCR1B - Timer/Counter1 Control Register B
|
||||
.equ CS10 = 0 ; Clock Select bit 0
|
||||
.equ CS11 = 1 ; Clock Select 1 bit 1
|
||||
.equ CS12 = 2 ; Clock Select1 bit 2
|
||||
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
|
||||
.equ CTC1 = WGM12 ; For compatibility
|
||||
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
|
||||
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
||||
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
||||
|
||||
; TCCR1C - Timer/Counter1 Control Register C
|
||||
.equ FOC1B = 6 ; Force Output Compare for Channel B
|
||||
.equ FOC1A = 7 ; Force Output Compare for Channel A
|
||||
|
||||
|
||||
; ***** WATCHDOG *********************
|
||||
; WDTCR - Watchdog Timer Control Register
|
||||
.equ WDTCSR = WDTCR ; For compatibility
|
||||
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||||
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||||
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||||
.equ WDE = 3 ; Watch Dog Enable
|
||||
.equ WDCE = 4 ; Watchdog Change Enable
|
||||
.equ WDTOE = WDCE ; For compatibility
|
||||
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
||||
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
|
||||
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
|
||||
|
||||
|
||||
; ***** USART ************************
|
||||
; UDR - USART I/O Data Register
|
||||
.equ UDR0 = 0 ; USART I/O Data Register bit 0
|
||||
.equ UDR1 = 1 ; USART I/O Data Register bit 1
|
||||
.equ UDR2 = 2 ; USART I/O Data Register bit 2
|
||||
.equ UDR3 = 3 ; USART I/O Data Register bit 3
|
||||
.equ UDR4 = 4 ; USART I/O Data Register bit 4
|
||||
.equ UDR5 = 5 ; USART I/O Data Register bit 5
|
||||
.equ UDR6 = 6 ; USART I/O Data Register bit 6
|
||||
.equ UDR7 = 7 ; USART I/O Data Register bit 7
|
||||
|
||||
; UCSRA - USART Control and Status Register A
|
||||
.equ USR = UCSRA ; For compatibility
|
||||
.equ MPCM = 0 ; Multi-processor Communication Mode
|
||||
.equ U2X = 1 ; Double the USART Transmission Speed
|
||||
.equ UPE = 2 ; USART Parity Error
|
||||
.equ PE = UPE ; For compatibility
|
||||
.equ DOR = 3 ; Data overRun
|
||||
.equ FE = 4 ; Framing Error
|
||||
.equ UDRE = 5 ; USART Data Register Empty
|
||||
.equ TXC = 6 ; USART Transmitt Complete
|
||||
.equ RXC = 7 ; USART Receive Complete
|
||||
|
||||
; UCSRB - USART Control and Status Register B
|
||||
.equ UCR = UCSRB ; For compatibility
|
||||
.equ TXB8 = 0 ; Transmit Data Bit 8
|
||||
.equ RXB8 = 1 ; Receive Data Bit 8
|
||||
.equ UCSZ2 = 2 ; Character Size
|
||||
.equ CHR9 = UCSZ2 ; For compatibility
|
||||
.equ TXEN = 3 ; Transmitter Enable
|
||||
.equ RXEN = 4 ; Receiver Enable
|
||||
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
|
||||
.equ TXCIE = 6 ; TX Complete Interrupt Enable
|
||||
.equ RXCIE = 7 ; RX Complete Interrupt Enable
|
||||
|
||||
; UCSRC - USART Control and Status Register C
|
||||
.equ UCPOL = 0 ; Clock Polarity
|
||||
.equ UCSZ0 = 1 ; Character Size Bit 0
|
||||
.equ UCSZ1 = 2 ; Character Size Bit 1
|
||||
.equ USBS = 3 ; Stop Bit Select
|
||||
.equ UPM0 = 4 ; Parity Mode Bit 0
|
||||
.equ UPM1 = 5 ; Parity Mode Bit 1
|
||||
.equ UMSEL0 = 6 ; USART Mode Select 0
|
||||
.equ UMSEL1 = 7 ; USART Mode Select 1
|
||||
.equ UCPHA = 1 ; USART MSPIM Clock Phase
|
||||
.equ UDORD = 2 ; USART MSPIM Data Order
|
||||
|
||||
.equ UBRR = UBRRL ; For compatibility
|
||||
|
||||
; ***** ANALOG_COMPARATOR ************
|
||||
; ACSR - Analog Comparator Control And Status Register
|
||||
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
|
||||
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
|
||||
.equ ACIC = 2 ;
|
||||
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
|
||||
.equ ACI = 4 ; Analog Comparator Interrupt Flag
|
||||
.equ ACO = 5 ; Analog Compare Output
|
||||
.equ ACBG = 6 ; Analog Comparator Bandgap Select
|
||||
.equ ACD = 7 ; Analog Comparator Disable
|
||||
|
||||
; DIDR - Digital Input Disable Register 1
|
||||
.equ AIN0D = 0 ; AIN0 Digital Input Disable
|
||||
.equ AIN1D = 1 ; AIN1 Digital Input Disable
|
||||
|
||||
|
||||
; ***** PORTD ************************
|
||||
; PORTD - Data Register, Port D
|
||||
.equ PORTD0 = 0 ;
|
||||
.equ PD0 = 0 ; For compatibility
|
||||
.equ PORTD1 = 1 ;
|
||||
.equ PD1 = 1 ; For compatibility
|
||||
.equ PORTD2 = 2 ;
|
||||
.equ PD2 = 2 ; For compatibility
|
||||
.equ PORTD3 = 3 ;
|
||||
.equ PD3 = 3 ; For compatibility
|
||||
.equ PORTD4 = 4 ;
|
||||
.equ PD4 = 4 ; For compatibility
|
||||
.equ PORTD5 = 5 ;
|
||||
.equ PD5 = 5 ; For compatibility
|
||||
.equ PORTD6 = 6 ;
|
||||
.equ PD6 = 6 ; For compatibility
|
||||
|
||||
; DDRD - Data Direction Register, Port D
|
||||
.equ DDD0 = 0 ;
|
||||
.equ DDD1 = 1 ;
|
||||
.equ DDD2 = 2 ;
|
||||
.equ DDD3 = 3 ;
|
||||
.equ DDD4 = 4 ;
|
||||
.equ DDD5 = 5 ;
|
||||
.equ DDD6 = 6 ;
|
||||
|
||||
; PIND - Input Pins, Port D
|
||||
.equ PIND0 = 0 ;
|
||||
.equ PIND1 = 1 ;
|
||||
.equ PIND2 = 2 ;
|
||||
.equ PIND3 = 3 ;
|
||||
.equ PIND4 = 4 ;
|
||||
.equ PIND5 = 5 ;
|
||||
.equ PIND6 = 6 ;
|
||||
|
||||
|
||||
; ***** EEPROM ***********************
|
||||
; EEAR - EEPROM Read/Write Access
|
||||
.equ EEARL = EEAR ; For compatibility
|
||||
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
|
||||
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
|
||||
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
|
||||
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
|
||||
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
|
||||
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
|
||||
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6
|
||||
|
||||
; EEDR - EEPROM Data Register
|
||||
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
||||
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
||||
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
||||
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
||||
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
||||
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
||||
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
||||
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
||||
|
||||
; EECR - EEPROM Control Register
|
||||
.equ EERE = 0 ; EEPROM Read Enable
|
||||
.equ EEPE = 1 ; EEPROM Write Enable
|
||||
.equ EEWE = EEPE ; For compatibility
|
||||
.equ EEMPE = 2 ; EEPROM Master Write Enable
|
||||
.equ EEMWE = EEMPE ; For compatibility
|
||||
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
|
||||
.equ EEPM0 = 4 ;
|
||||
.equ EEPM1 = 5 ;
|
||||
|
||||
|
||||
; ***** PORTA ************************
|
||||
; PORTA - Port A Data Register
|
||||
.equ PORTA0 = 0 ; Port A Data Register bit 0
|
||||
.equ PA0 = 0 ; For compatibility
|
||||
.equ PORTA1 = 1 ; Port A Data Register bit 1
|
||||
.equ PA1 = 1 ; For compatibility
|
||||
.equ PORTA2 = 2 ; Port A Data Register bit 2
|
||||
.equ PA2 = 2 ; For compatibility
|
||||
|
||||
; DDRA - Port A Data Direction Register
|
||||
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
|
||||
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
|
||||
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
|
||||
|
||||
; PINA - Port A Input Pins
|
||||
.equ PINA0 = 0 ; Input Pins, Port A bit 0
|
||||
.equ PINA1 = 1 ; Input Pins, Port A bit 1
|
||||
.equ PINA2 = 2 ; Input Pins, Port A bit 2
|
||||
|
||||
|
||||
; ***** USI **************************
|
||||
; USIDR - USI Data Register
|
||||
.equ USIDR0 = 0 ; USI Data Register bit 0
|
||||
.equ USIDR1 = 1 ; USI Data Register bit 1
|
||||
.equ USIDR2 = 2 ; USI Data Register bit 2
|
||||
.equ USIDR3 = 3 ; USI Data Register bit 3
|
||||
.equ USIDR4 = 4 ; USI Data Register bit 4
|
||||
.equ USIDR5 = 5 ; USI Data Register bit 5
|
||||
.equ USIDR6 = 6 ; USI Data Register bit 6
|
||||
.equ USIDR7 = 7 ; USI Data Register bit 7
|
||||
|
||||
; USISR - USI Status Register
|
||||
.equ USICNT0 = 0 ; USI Counter Value Bit 0
|
||||
.equ USICNT1 = 1 ; USI Counter Value Bit 1
|
||||
.equ USICNT2 = 2 ; USI Counter Value Bit 2
|
||||
.equ USICNT3 = 3 ; USI Counter Value Bit 3
|
||||
.equ USIDC = 4 ; Data Output Collision
|
||||
.equ USIPF = 5 ; Stop Condition Flag
|
||||
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
|
||||
.equ USISIF = 7 ; Start Condition Interrupt Flag
|
||||
|
||||
; USICR - USI Control Register
|
||||
.equ USITC = 0 ; Toggle Clock Port Pin
|
||||
.equ USICLK = 1 ; Clock Strobe
|
||||
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
|
||||
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
|
||||
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
|
||||
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
|
||||
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
|
||||
.equ USISIE = 7 ; Start Condition Interrupt Enable
|
||||
|
||||
|
||||
; ***** EXTERNAL_INTERRUPT ***********
|
||||
; GIMSK - General Interrupt Mask Register
|
||||
.equ PCIE1 = 3 ;
|
||||
.equ PCIE2 = 4 ;
|
||||
.equ PCIE0 = 5 ;
|
||||
.equ INT0 = 6 ; External Interrupt Request 0 Enable
|
||||
.equ INT1 = 7 ; External Interrupt Request 1 Enable
|
||||
|
||||
; EIFR - Extended Interrupt Flag Register
|
||||
.equ GIFR = EIFR ; For compatibility
|
||||
.equ PCIF0 = 5 ;
|
||||
.equ PCIF2 = 4 ;
|
||||
.equ PCIF1 = 3 ;
|
||||
.equ INTF0 = 6 ; External Interrupt Flag 0
|
||||
.equ INTF1 = 7 ; External Interrupt Flag 1
|
||||
|
||||
; PCMSK2 - Pin Change Interrupt Mask Register 2
|
||||
.equ PCINT11 = 0 ; Pin Change Interrupt Mask 11
|
||||
.equ PCINT12 = 1 ; Pin Change Interrupt Mask 12
|
||||
.equ PCINT13 = 2 ; Pin Change Interrupt Mask 13
|
||||
.equ PCINT14 = 3 ; Pin Change Interrupt Mask 14
|
||||
.equ PCINT15 = 4 ; Pin Change Interrupt Mask 15
|
||||
.equ PCINT16 = 5 ; Pin Change Interrupt Mask 16
|
||||
.equ PCINT17 = 6 ; Pin Change Interrupt Mask 17
|
||||
|
||||
; PCMSK1 - Pin Change Interrupt Mask Register 1
|
||||
.equ PCINT8 = 0 ; Pin Change Interrupt Mask 8
|
||||
.equ PCINT9 = 1 ; Pin Change Interrupt Mask 9
|
||||
.equ PCINT10 = 2 ; Pin Change Interrupt Mask 10
|
||||
|
||||
|
||||
; ***** CPU **************************
|
||||
; SREG - Status Register
|
||||
.equ SREG_C = 0 ; Carry Flag
|
||||
.equ SREG_Z = 1 ; Zero Flag
|
||||
.equ SREG_N = 2 ; Negative Flag
|
||||
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
||||
.equ SREG_S = 4 ; Sign Bit
|
||||
.equ SREG_H = 5 ; Half Carry Flag
|
||||
.equ SREG_T = 6 ; Bit Copy Storage
|
||||
.equ SREG_I = 7 ; Global Interrupt Enable
|
||||
|
||||
; SPMCSR - Store Program Memory Control and Status register
|
||||
.equ SPMEN = 0 ; Store Program Memory Enable
|
||||
.equ PGERS = 1 ; Page Erase
|
||||
.equ PGWRT = 2 ; Page Write
|
||||
.equ RFLB = 3 ; Read Fuse and Lock Bits
|
||||
.equ CTPB = 4 ; Clear Temporary Page Buffer
|
||||
|
||||
; MCUCR - MCU Control Register
|
||||
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
|
||||
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
|
||||
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0
|
||||
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1
|
||||
.equ SM0 = 4 ; Sleep Mode Select Bit 0
|
||||
.equ SM = SM0 ; For compatibility
|
||||
.equ SE = 5 ; Sleep Enable
|
||||
.equ SM1 = 6 ; Sleep Mode Select Bit 1
|
||||
.equ PUD = 7 ; Pull-up Disable
|
||||
|
||||
; CLKPR - Clock Prescale Register
|
||||
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
||||
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
||||
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
||||
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
||||
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
||||
|
||||
; MCUSR - MCU Status register
|
||||
.equ PORF = 0 ; Power-On Reset Flag
|
||||
.equ EXTRF = 1 ; External Reset Flag
|
||||
.equ BORF = 2 ; Brown-out Reset Flag
|
||||
.equ WDRF = 3 ; Watchdog Reset Flag
|
||||
|
||||
; OSCCAL - Oscillator Calibration Register
|
||||
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
|
||||
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
|
||||
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
|
||||
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
|
||||
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
|
||||
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
|
||||
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
|
||||
|
||||
; GTCCR - General Timer Counter Control Register
|
||||
.equ SFIOR = GTCCR ; For compatibility
|
||||
.equ PSR10 = 0 ;
|
||||
|
||||
; PCMSK - Pin-Change Mask register
|
||||
.equ PCINT0 = 0 ; Pin-Change Interrupt 0
|
||||
.equ PCINT1 = 1 ; Pin-Change Interrupt 1
|
||||
.equ PCINT2 = 2 ; Pin-Change Interrupt 2
|
||||
.equ PCINT3 = 3 ; Pin-Change Interrupt 3
|
||||
.equ PCINT4 = 4 ; Pin-Change Interrupt 4
|
||||
.equ PCINT5 = 5 ; Pin-Change Interrupt 5
|
||||
.equ PCINT6 = 6 ; Pin-Change Interrupt 6
|
||||
.equ PCINT7 = 7 ; Pin-Change Interrupt 7
|
||||
|
||||
; GPIOR2 - General Purpose I/O Register 2
|
||||
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0
|
||||
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1
|
||||
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2
|
||||
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3
|
||||
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4
|
||||
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5
|
||||
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6
|
||||
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7
|
||||
|
||||
; GPIOR1 - General Purpose I/O Register 1
|
||||
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0
|
||||
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1
|
||||
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2
|
||||
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3
|
||||
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4
|
||||
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5
|
||||
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6
|
||||
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7
|
||||
|
||||
; GPIOR0 - General Purpose I/O Register 0
|
||||
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0
|
||||
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1
|
||||
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2
|
||||
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3
|
||||
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4
|
||||
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5
|
||||
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6
|
||||
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7
|
||||
|
||||
; PRR - Power reduction register
|
||||
.equ PRUSART = 0 ;
|
||||
.equ PRUSI = 1 ;
|
||||
.equ PRTIM0 = 2 ;
|
||||
.equ PRTIM1 = 3 ;
|
||||
|
||||
; BODCR - BOD control register
|
||||
.equ BPDSE = 0 ;
|
||||
.equ BPDS = 1 ;
|
||||
|
||||
|
||||
|
||||
; ***** LOCKSBITS ********************************************************
|
||||
.equ LB1 = 0 ; Lockbit
|
||||
.equ LB2 = 1 ; Lockbit
|
||||
|
||||
|
||||
; ***** FUSES ************************************************************
|
||||
; LOW fuse bits
|
||||
.equ CKSEL0 = 0 ; Select Clock Source
|
||||
.equ CKSEL1 = 1 ; Select Clock Source
|
||||
.equ CKSEL2 = 2 ; Select Clock Source
|
||||
.equ CKSEL3 = 3 ; Select Clock Source
|
||||
.equ SUT0 = 4 ; Select start-up time
|
||||
.equ SUT1 = 5 ; Select start-up time
|
||||
.equ CKOUT = 6 ; Clock output
|
||||
.equ CKDIV8 = 7 ; Divide clock by 8
|
||||
|
||||
; HIGH fuse bits
|
||||
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
||||
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
||||
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
||||
.equ WDTON = 4 ; Watchdog Timer Always On
|
||||
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
||||
.equ DWEN = 6 ; debugWIRE Enable
|
||||
.equ RSTDISBL = 7 ; External reset disable
|
||||
|
||||
; EXTENDED fuse bits
|
||||
.equ SELFPRGEN = 0 ; Self Programming Enable
|
||||
|
||||
|
||||
|
||||
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||||
.def XH = r27
|
||||
.def XL = r26
|
||||
.def YH = r29
|
||||
.def YL = r28
|
||||
.def ZH = r31
|
||||
.def ZL = r30
|
||||
|
||||
|
||||
|
||||
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||||
.equ FLASHEND = 0x03ff ; Note: Word address
|
||||
.equ IOEND = 0x003f
|
||||
.equ SRAM_START = 0x0060
|
||||
.equ SRAM_SIZE = 128
|
||||
.equ RAMEND = 0x00df
|
||||
.equ XRAMEND = 0x0000
|
||||
.equ E2END = 0x007f
|
||||
.equ EEPROMEND = 0x007f
|
||||
.equ EEADRBITS = 7
|
||||
#pragma AVRPART MEMORY PROG_FLASH 2048
|
||||
#pragma AVRPART MEMORY EEPROM 128
|
||||
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
||||
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||||
|
||||
|
||||
|
||||
; ***** BOOTLOADER DECLARATIONS ******************************************
|
||||
.equ NRWW_START_ADDR = 0x0
|
||||
.equ NRWW_STOP_ADDR = 0x3ff
|
||||
.equ RWW_START_ADDR = 0x0
|
||||
.equ RWW_STOP_ADDR = 0x0
|
||||
.equ PAGESIZE = 16
|
||||
|
||||
|
||||
|
||||
; ***** INTERRUPT VECTORS ************************************************
|
||||
.equ INT0addr = 0x0001 ; External Interrupt Request 0
|
||||
.equ INT1addr = 0x0002 ; External Interrupt Request 1
|
||||
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event
|
||||
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A
|
||||
.equ OC1addr = 0x0004 ; For compatibility
|
||||
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow
|
||||
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow
|
||||
.equ URXCaddr = 0x0007 ; USART, Rx Complete
|
||||
.equ URXC0addr = 0x0007 ; For compatibility
|
||||
.equ UDREaddr = 0x0008 ; USART Data Register Empty
|
||||
.equ UDRE0addr = 0x0008 ; For compatibility
|
||||
.equ UTXCaddr = 0x0009 ; USART, Tx Complete
|
||||
.equ UTXC0addr = 0x0009 ; For compatibility
|
||||
.equ ACIaddr = 0x000a ; Analog Comparator
|
||||
.equ PCIBaddr = 0x000b ; Pin Change Interrupt Request B
|
||||
.equ PCIaddr = 0x000b ; For compatibility
|
||||
.equ OC1Baddr = 0x000c ;
|
||||
.equ OC0Aaddr = 0x000d ;
|
||||
.equ OC0Baddr = 0x000e ;
|
||||
.equ USI_STARTaddr = 0x000f ; USI Start Condition
|
||||
.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
||||
.equ ERDYaddr = 0x0011 ;
|
||||
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow
|
||||
.equ PCIAaddr = 0x0013 ; Pin Change Interrupt Request A
|
||||
.equ PCIDaddr = 0x0014 ; Pin Change Interrupt Request D
|
||||
|
||||
.equ INT_VECTORS_SIZE = 21 ; size in words
|
||||
|
||||
#endif /* _TN2313ADEF_INC_ */
|
||||
|
||||
; ***** END OF FILE ******************************************************
|
||||
Loading…
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Reference in New Issue
Block a user