bubble/attiny24a_memory-led-game
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refactored

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This commit is contained in:
Sergey Yarkov 2022-05-25 23:51:13 +03:00
parent 26143bef1a
commit 079637a034
3 changed files with 1245 additions and 1094 deletions
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244
firmware.asm
View File

@ -16,6 +16,7 @@
; ;
; Registers ; Registers
.def seq_length_r = r10 ; Current length of sequence .def seq_length_r = r10 ; Current length of sequence
.def wdt_counter = r11 ; Counter for wathdog timer
.def temp_r = r16 ; Temp general register A .def temp_r = r16 ; Temp general register A
.def temp_r_b = r23 ; Temp general register B .def temp_r_b = r23 ; Temp general register B
.def temp_r_c = r26 ; Temp general register C .def temp_r_c = r26 ; Temp general register C
@ -75,25 +76,22 @@
.dseg ; Data segment .dseg ; Data segment
.org SRAM_START .org SRAM_START
;
; MCU Global states addresses ; MCU Global states addresses
CURRENT_STATE_ADDRESS: .byte 0x01 CURRENT_STATE_ADDRESS: .byte 0x01
PREVIOUS_STATE_ADDRESS: .byte 0x01 PREVIOUS_STATE_ADDRESS: .byte 0x01
;
; Button flags ; Button flags
SW_FLAGS_ADDRESS: .byte 0x01 SW_FLAGS_ADDRESS: .byte 0x01
.cseg ; Code segment .cseg ; Code segment
.org 0x00 .org 0x00
; ; MCU vectors
; Setup vectors rjmp RESET_vect ; Program start at RESET vector
rjmp start ; Program start at RESET vector
reti ; External Interrupt Request 0 / inactive reti ; External Interrupt Request 0 / inactive
rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active
reti ; Pin Change Interrupt Request 1 / inactive reti ; Pin Change Interrupt Request 1 / inactive
reti ; Watchdog Time-out / inactive rjmp WDT_vect ; Watchdog Time-out / active
reti ; Timer/Counter1 Capture Event / inactive reti ; Timer/Counter1 Capture Event / inactive
reti ; Timer/Counter1 Compare Match A / inactive reti ; Timer/Counter1 Compare Match A / inactive
reti ; Timer/Counter1 Compare Match B / inactive reti ; Timer/Counter1 Compare Match B / inactive
@ -107,27 +105,44 @@ reti ; EEPROM Ready / inactive
reti ; USI START / inactive reti ; USI START / inactive
reti ; USI Overflow / inactive reti ; USI Overflow / inactive
; ; watchdog time-out interrupt handler
; Interrupt service routines WDT_vect:
PCINT0_vect: ; Button handler in temp_r_c, WDTCSR
ldi temp_r_c, (1<<WDIE)
out WDTCSR, temp_r_c
inc wdt_counter
reti
; pin change on button interrupt handler
PCINT0_vect:
push r17 push r17
push r18 push r18
in r18, SREG ; Save status register in r18, MCUCR
cbr r18, (1<<SE)
; turn off the sleep mode
out MCUCR, r18
; save status register
in r18, SREG
lds mcu_state_r, CURRENT_STATE_ADDRESS lds mcu_state_r, CURRENT_STATE_ADDRESS
cpi mcu_state_r, POLLING_STATE cpi mcu_state_r, POLLING_STATE
brne quit ; Do not change button flags unless in POLLING state of mcu ; do not change button flags unless in POLLING state of mcu
in r17, PINA ; Load current pins status of PINA brne quit
andi r17, 0xf0 ; Get pins status of only buttons in r17, PINA
rcall delay_20ms ; Delay for button ; get pins status of only buttons
sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM andi r17, 0xf0
; button debounce
rcall delay_20ms
; update flag status in SRAM
sts SW_FLAGS_ADDRESS, r17
out SREG, r18 out SREG, r18
quit: quit:
pop r18 pop r18
pop r17 pop r17
reti reti
TIM0_OVF_vect: ; Random byte generator ; random byte generator
TIM0_OVF_vect:
push temp_r_b push temp_r_b
in temp_r_b, SREG in temp_r_b, SREG
@ -142,15 +157,17 @@ TIM0_OVF_vect: ; Random byte generator
add r21, temp_r add r21, temp_r
out SREG, temp_r_b out SREG, temp_r_b
pop temp_r_b pop temp_r_b
reti reti
MCU_Init: ; This function executes once on start the main program ; initialize MCU
MCU_Init:
rcall init_ports rcall init_ports
rcall init_interrupts rcall init_interrupts
rcall init_buzzer rcall init_buzzer
rcall init_sm
; rcall init_wdt
; ; init important registers for game
; Init important registers for game
ldi delay_counter_r, 0xff ldi delay_counter_r, 0xff
ldi poll_step_r, 1 ldi poll_step_r, 1
ldi temp_r_c, SEQ_LENGTH ldi temp_r_c, SEQ_LENGTH
@ -158,10 +175,11 @@ MCU_Init: ; This function executes once on start the main program
clr ZH clr ZH
ldi ZL, $80 ldi ZL, $80
rcall MCU_Delay ; Wait 1 sec before start main program ; delay before start main loop
rcall MCU_Delay
sei ; Enable Global Interrupts sei
ret ret
MCU_Delay: MCU_Delay:
ldi temp_r_b, 3 ldi temp_r_b, 3
@ -171,33 +189,39 @@ MCU_Delay:
brne _init_loop_loading brne _init_loop_loading
rcall delay_1s rcall delay_1s
clr temp_r_b clr temp_r_b
ret ret
; ; program start at reset vector
; Program start at reset RESET_vect:
start:
init_stack_p temp_r, RAMEND init_stack_p temp_r, RAMEND
set_state INIT_STATE set_state INIT_STATE
loop: ; Program loop
; main program loop
loop:
lds mcu_state_r, CURRENT_STATE_ADDRESS lds mcu_state_r, CURRENT_STATE_ADDRESS
init: ; Init state ; init state
init:
cpi mcu_state_r, INIT_STATE cpi mcu_state_r, INIT_STATE
brne showing brne showing
rcall MCU_Init rcall MCU_Init
set_state SHOWING_STATE set_state SHOWING_STATE
showing: ; Showing state
; showing state
showing:
cpi mcu_state_r, SHOWING_STATE cpi mcu_state_r, SHOWING_STATE
brne polling brne polling
rcall show_sequence ; Generate sequence and save answer to SRAM ; generate sequence and save answer to SRAM
rcall show_sequence
set_state POLLING_STATE set_state POLLING_STATE
polling: ; Polling state
; polling state
polling:
cpi mcu_state_r, POLLING_STATE cpi mcu_state_r, POLLING_STATE
brne default brne default
btn_1: btn_1:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_1 cpi r18, SW_FLAG_1
brne btn_2 ; Check next button brne btn_2
led_on_1: led_on_1:
outi OCR0A, 142 outi OCR0A, 142
sbi LED_PORT, 0 sbi LED_PORT, 0
@ -206,6 +230,7 @@ loop: ; Program loop
cbi LED_PORT, 0 cbi LED_PORT, 0
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
rjmp btn_1 rjmp btn_1
btn_2: btn_2:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_2 cpi r18, SW_FLAG_2
@ -218,6 +243,7 @@ loop: ; Program loop
cbi LED_PORT, 1 cbi LED_PORT, 1
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
rjmp btn_2 rjmp btn_2
btn_3: btn_3:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_3 cpi r18, SW_FLAG_3
@ -230,6 +256,7 @@ loop: ; Program loop
cbi LED_PORT, 2 cbi LED_PORT, 2
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
rjmp btn_3 rjmp btn_3
btn_4: btn_4:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_4 cpi r18, SW_FLAG_4
@ -242,12 +269,13 @@ loop: ; Program loop
cbi LED_PORT, 3 cbi LED_PORT, 3
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
rjmp btn_4 rjmp btn_4
default: default:
rcall OCR0A_reset rcall OCR0A_reset
rjmp loop rjmp loop
; check the input value with answer in SRAM
btn_handler: ; Check the input value with answer in SRAM btn_handler:
push r18 push r18
rcall delay_50ms rcall delay_50ms
rcall delay_50ms rcall delay_50ms
@ -260,8 +288,10 @@ btn_handler: ; Check the input value with answer in SRAM
sts SW_FLAGS_ADDRESS, temp_r_c sts SW_FLAGS_ADDRESS, temp_r_c
ld r24, Z+ ld r24, Z+
cp r25, r24 ; Check answer ; check answer
brne _game_over ; Game over cp r25, r24
; game over
brne _game_over
mov r18, seq_length_r mov r18, seq_length_r
cp r18, poll_step_r cp r18, poll_step_r
@ -290,10 +320,11 @@ btn_handler: ; Check the input value with answer in SRAM
rcall effect_2 rcall effect_2
rcall reset_game rcall reset_game
ret ret
_btn_handler_exit: _btn_handler_exit:
pop r18 pop r18
ret ret
ret ret
reset_game: reset_game:
clr ZH clr ZH
@ -305,49 +336,53 @@ reset_game:
set_state SHOWING_STATE set_state SHOWING_STATE
ldi poll_step_r, 1 ldi poll_step_r, 1
inc seq_length_r inc seq_length_r
ret ret
gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM ; generate random sequence of bytes for leds and save answer to SRAM
gen_ran_seq:
mov temp_r_b, seq_length_r mov temp_r_b, seq_length_r
clr YH clr YH
ldi YL, $80 ldi YL, $80
_gen_ran_loop:
rcall delay_50ms ; Delay is required!
mov r22, r21
_gen_ran_loop:
; delay is required
rcall delay_50ms
mov r22, r21
cpi r22, 70 cpi r22, 70
brlo _gen_answ_1 brlo _gen_answ_1
cpi r22, 140 cpi r22, 140
brlo _gen_answ_2 brlo _gen_answ_2
cpi r22, 200 cpi r22, 200
brlo _gen_answ_3 brlo _gen_answ_3
cpi r22, 255 cpi r22, 255
brlo _gen_answ_4 brlo _gen_answ_4
_gen_answ_1: _gen_answ_1:
ldi temp_r_c, 0x01 ldi temp_r_c, 0x01
rjmp _gen_ran_write rjmp _gen_ran_write
_gen_answ_2: _gen_answ_2:
ldi temp_r_c, 0x02 ldi temp_r_c, 0x02
rjmp _gen_ran_write rjmp _gen_ran_write
_gen_answ_3: _gen_answ_3:
ldi temp_r_c, 0x04 ldi temp_r_c, 0x04
rjmp _gen_ran_write rjmp _gen_ran_write
_gen_answ_4: _gen_answ_4:
ldi temp_r_c, 0x08 ldi temp_r_c, 0x08
_gen_ran_write: _gen_ran_write:
st Y+, temp_r_c st Y+, temp_r_c
dec temp_r_b dec temp_r_b
cpi temp_r_b, 0 cpi temp_r_b, 0
brne _gen_ran_loop brne _gen_ran_loop
nop nop
ret ret
show_sequence: show_sequence:
rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} ; answer stored in SRAM in addr $80:{SEQ_LENGTH}
rcall gen_ran_seq
show_start: show_start:
mov temp_r_b, seq_length_r mov temp_r_b, seq_length_r
@ -357,17 +392,13 @@ show_sequence:
_sequence_loop: _sequence_loop:
cpi temp_r_b, 0 cpi temp_r_b, 0
breq _seq_quit breq _seq_quit
ld temp_r_c, Y+ ld temp_r_c, Y+
cpi temp_r_c, 0x01 cpi temp_r_c, 0x01
breq beep_1 breq beep_1
cpi temp_r_c, 0x02 cpi temp_r_c, 0x02
breq beep_2 breq beep_2
cpi temp_r_c, 0x04 cpi temp_r_c, 0x04
breq beep_3 breq beep_3
cpi temp_r_c, 0x08 cpi temp_r_c, 0x08
breq beep_4 breq beep_4
@ -375,17 +406,21 @@ show_sequence:
beep_led_1 beep_led_1
rcall OCR0A_reset rcall OCR0A_reset
rjmp beep_quit rjmp beep_quit
beep_2: beep_2:
beep_led_2 beep_led_2
rcall OCR0A_reset rcall OCR0A_reset
rjmp beep_quit rjmp beep_quit
beep_3: beep_3:
beep_led_3 beep_led_3
rcall OCR0A_reset rcall OCR0A_reset
rjmp beep_quit rjmp beep_quit
beep_4: beep_4:
beep_led_4 beep_led_4
rcall OCR0A_reset rcall OCR0A_reset
beep_quit: beep_quit:
rcall delay rcall delay
dec temp_r_b dec temp_r_b
@ -395,14 +430,20 @@ show_sequence:
_seq_quit: _seq_quit:
rcall dec_delay_counter rcall dec_delay_counter
rcall delay_50ms rcall delay_50ms
ret
OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt ; in temp_r_c, MCUCR
; sbr temp_r_c, (1<<SE)
; out MCUCR, temp_r_c
; sleep
ret
; this function need to set the OCR0A register to 0xff for overflow interrupt
OCR0A_reset:
push temp_r_b push temp_r_b
ldi temp_r_b, 0xff ldi temp_r_b, 0xff
out OCR0A, temp_r_b out OCR0A, temp_r_b
pop temp_r_b pop temp_r_b
ret ret
dec_delay_counter: dec_delay_counter:
subi delay_counter_r, 10 subi delay_counter_r, 10
@ -411,13 +452,14 @@ dec_delay_counter:
ret ret
_reset_counter: _reset_counter:
ldi delay_counter_r, 0xff ldi delay_counter_r, 0xff
ret ret
effect_1: ; Shift bits of an leds in port every 50ms effect_1: ; Shift bits of an leds in port every 50ms
push r17 push r17
push r18 push r18
push r19 push r19
push r20 push r20
cli cli
in r20, LED_PORT in r20, LED_PORT
@ -425,7 +467,9 @@ effect_1: ; Shift bits of an leds in port every 50ms
rcall delay_50ms rcall delay_50ms
ldi r17, 0x01 ldi r17, 0x01
ldi r19, 3 ldi r19, 3
_eff_1_shift_l: ; Shift bits to left loop
; shift bits to left loop
_eff_1_shift_l:
ldi r18, 0xf0 ldi r18, 0xf0
lsl r17 lsl r17
add r18, r17 add r18, r17
@ -438,7 +482,9 @@ effect_1: ; Shift bits of an leds in port every 50ms
rcall delay_50ms rcall delay_50ms
ldi r17, 0x08 ldi r17, 0x08
ldi r19, 3 ldi r19, 3
_eff_1_shift_r: ; Shift bits to right loop
; shift bits to right loop
_eff_1_shift_r:
ldi r18, 0xf0 ldi r18, 0xf0
lsr r17 lsr r17
add r18, r17 add r18, r17
@ -448,13 +494,14 @@ effect_1: ; Shift bits of an leds in port every 50ms
brne _eff_1_shift_r brne _eff_1_shift_r
sei sei
; Out saved PORT values
; out saved PORT values
out LED_PORT, r20 out LED_PORT, r20
pop r20 pop r20
pop r19 pop r19
pop r18 pop r18
pop r17 pop r17
ret ret
effect_2: effect_2:
outi OCR0A, 142 outi OCR0A, 142
@ -488,49 +535,75 @@ effect_2:
rcall delay_50ms rcall delay_50ms
cbi LED_PORT, 3 cbi LED_PORT, 3
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
ret ret
init_interrupts: init_interrupts:
; ; enable Port Change Interrupt
; Enable Port Change Interrupt
ldi temp_r, (1<<PCIE0) ldi temp_r, (1<<PCIE0)
out GIMSK, temp_r out GIMSK, temp_r
; ; set Pin Change Mask Register
; Set Pin Change Mask Register
ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7) ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7)
out PCMSK0, temp_r out PCMSK0, temp_r
clr temp_r clr temp_r
ret ret
init_buzzer: init_buzzer:
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
; Setup timer ; setup timer
ldi temp_r, (1<<COM0A0) | (1<<WGM01) ; Set CTC timer mode and toggle OC0A pin on Compare Match ldi temp_r, (1<<COM0A0) | (1<<WGM01)
; set CTC timer mode and toggle OC0A pin on Compare Match
out TCCR0A, temp_r out TCCR0A, temp_r
ldi temp_r, 255 ldi temp_r, 255
out OCR0A, temp_r out OCR0A, temp_r
ldi temp_r, (1<<CS01) ; Prescale on 8 ldi temp_r, (1<<CS01)
; prescale on 8
out TCCR0B, temp_r out TCCR0B, temp_r
ldi temp_r, (1<<TOIE0) ; Enable Timer/Counter0 Overflow Interrupt ldi temp_r, (1<<TOIE0)
; enable Timer/Counter0 Overflow Interrupt
out TIMSK0, temp_r out TIMSK0, temp_r
ret ret
init_ports: ; Init MCU ports init_ports: ; Init MCU ports
ldi temp_r, 0x0f ; Setup PORTA ; setup PORTA
out DDRA, temp_r ; Set directions of leds and buttons ldi temp_r, 0x0f
; set directions of leds and buttons
out DDRA, temp_r
swap temp_r swap temp_r
out PORTA, temp_r ; Set low signal on leds and pull-up on buttons ; set low signal on leds and pull-up on buttons
out PORTA, temp_r
; Setup PORTB ; setup PORTB
sbi DDRB, BUZZ_PIN ; Set direction of buzzer pin to output sbi DDRB, BUZZ_PIN ; Set direction of buzzer pin to output
cbi PORTB, BUZZ_PIN ; Set low signal on buzzer cbi PORTB, BUZZ_PIN ; Set low signal on buzzer
ret ret
init_sm:
in temp_r, MCUCR
ori temp_r, (1<<SM1)
; config sleep mode to power-down
out MCUCR, temp_r
ret
init_wdt:
cli
wdr
in temp_r, WDTCSR
ori temp_r, (1<<WDCE) | (1<<WDE)
; allow changing the watchdog bits and enable watchdog
out WDTCSR, temp_r
ldi temp_r, (1<<WDE) | (1<<WDIE) | (1<<WDP2) | (1<<WDP0)
; config watchdog to interrupt mode and setup prescaler (0.5 sec)
out WDTCSR, temp_r
sei
ret
delay: ; For 1MHz frequency delay: ; For 1MHz frequency
push r18 push r18
@ -547,7 +620,7 @@ delay: ; For 1MHz frequency
nop nop
pop r20 pop r20
pop r18 pop r18
ret ret
delay_20ms: delay_20ms:
push r18 push r18
@ -562,7 +635,7 @@ delay_20ms:
brne _loop_d_20ms brne _loop_d_20ms
pop r19 pop r19
pop r18 pop r18
ret ret
delay_50ms: ; For 1MHz frequency delay_50ms: ; For 1MHz frequency
push r18 push r18
@ -578,20 +651,21 @@ delay_50ms: ; For 1MHz frequency
nop nop
pop r19 pop r19
pop r18 pop r18
ret ret
delay_1s: ; For 1MHz frequency delay_1s: ; For 1MHz frequency
push r24 push r24
push r25 push r25
.equ outer_count = 100 .equ outer_count = 100
.equ inner_count = 2499 .equ inner_count = 2499
ldi r18, outer_count ldi r18, outer_count
_reset: _reset:
ldi r24, low(inner_count) ldi r24, low(inner_count)
ldi r25, high(inner_count) ldi r25, high(inner_count)
_loop: _loop:
sbiw r24, 1 sbiw r24, 1
brne _loop brne _loop
dec r18 dec r18
@ -599,6 +673,6 @@ _loop:
ldi r18, outer_count ldi r18, outer_count
pop r25 pop r25
pop r24 pop r24
ret ret
info: .db "Memory led game. Written by Sergey Yarkov 27.09.2021" info: .db "Memory led game. Written by Sergey Yarkov 27.09.2021"

127
firmware.hex
View File

@ -1,64 +1,67 @@
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