From 26143bef1acba7a3e281fd893e7615eaa1c6f438 Mon Sep 17 00:00:00 2001 From: Sergey Yarkov Date: Sun, 22 May 2022 21:07:15 +0300 Subject: [PATCH] feat: next lvl effect --- firmware.asm | 83 ++++++- firmware.hex | 84 +++---- firmware.lss | 627 ++++++++++++++++++++++++++++----------------------- 3 files changed, 468 insertions(+), 326 deletions(-) diff --git a/firmware.asm b/firmware.asm index 7c304f7..707af04 100644 --- a/firmware.asm +++ b/firmware.asm @@ -118,7 +118,7 @@ PCINT0_vect: ; Button handler brne quit ; Do not change button flags unless in POLLING state of mcu in r17, PINA ; Load current pins status of PINA andi r17, 0xf0 ; Get pins status of only buttons - rcall delay_50ms ; Delay for button + rcall delay_20ms ; Delay for button sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM out SREG, r18 @@ -268,33 +268,45 @@ btn_handler: ; Check the input value with answer in SRAM breq _btn_handler_exit_state inc poll_step_r - + rjmp _btn_handler_exit _game_over: + pop r18 rcall effect_1 ldi delay_counter_r, 0xff ldi temp_r_c, SEQ_LENGTH dec temp_r_c mov seq_length_r, temp_r_c + rcall reset_game + ret _btn_handler_exit_state: pop r18 - clr ZH - ldi ZL, $80 - cbi BUZZ_DIR, BUZZ_PIN - ldi temp_r, 0xf0 - out LED_PORT, temp_r - rcall delay_1s - set_state SHOWING_STATE - ldi poll_step_r, 1 - inc seq_length_r + ldi temp_r, 0xf0 + out LED_PORT, temp_r + cbi BUZZ_DIR, BUZZ_PIN + rcall delay_50ms + rcall effect_2 + rcall reset_game ret _btn_handler_exit: pop r18 ret ret +reset_game: + clr ZH + ldi ZL, $80 + cbi BUZZ_DIR, BUZZ_PIN + ldi temp_r, 0xf0 + out LED_PORT, temp_r + rcall delay_1s + set_state SHOWING_STATE + ldi poll_step_r, 1 + inc seq_length_r +ret + gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM mov temp_r_b, seq_length_r clr YH @@ -444,6 +456,40 @@ effect_1: ; Shift bits of an leds in port every 50ms pop r17 ret +effect_2: + outi OCR0A, 142 + sbi LED_PORT, 0 + sbi BUZZ_DIR, BUZZ_PIN + rcall delay_50ms + rcall delay_50ms + cbi LED_PORT, 0 + cbi BUZZ_DIR, BUZZ_PIN + + outi OCR0A, 105 + sbi LED_PORT, 1 + sbi BUZZ_DIR, BUZZ_PIN + rcall delay_50ms + rcall delay_50ms + cbi LED_PORT, 1 + cbi BUZZ_DIR, BUZZ_PIN + + outi OCR0A, 80 + sbi LED_PORT, 2 + sbi BUZZ_DIR, BUZZ_PIN + rcall delay_50ms + rcall delay_50ms + cbi LED_PORT, 2 + cbi BUZZ_DIR, BUZZ_PIN + + outi OCR0A, 71 + sbi LED_PORT, 3 + sbi BUZZ_DIR, BUZZ_PIN + rcall delay_50ms + rcall delay_50ms + cbi LED_PORT, 3 + cbi BUZZ_DIR, BUZZ_PIN +ret + init_interrupts: ; ; Enable Port Change Interrupt @@ -503,6 +549,21 @@ delay: ; For 1MHz frequency pop r18 ret +delay_20ms: + push r18 + push r19 + + ldi r18, 26 + ldi r19, 249 + _loop_d_20ms: + dec r19 + brne _loop_d_20ms + dec r18 + brne _loop_d_20ms + pop r19 + pop r18 +ret + delay_50ms: ; For 1MHz frequency push r18 push r19 diff --git a/firmware.hex b/firmware.hex index 4079da0..feaaf58 100644 --- a/firmware.hex +++ b/firmware.hex @@ -2,14 +2,14 @@ :100000003EC018950EC01895189518951895189516 :1000100018951895189515C0189518951895189550 :1000200018951F932F932FB710916000133031F460 -:1000300019B3107F60D1109362002FBF2F911F91D1 +:1000300019B3107F93D1109362002FBF2F911F919E :1000400018957F937FB702C008EA52B7052702953B -:10005000500F7FBF7F91189539D128D12DD13FEF17 +:10005000500F7FBF7F9118956CD15BD160D13FEF7E :1000600041E0A2E0AA2EFF27E0E802D078940895AC -:1000700073E0F3D07A95E9F74AD1772708950FED29 +:1000700073E0FDD07A95E9F788D1772708950FEDE1 :100080000DBF0027109361000F9301E00093600003 :100090000F9110916000113041F4DEDF1093610088 -:1000A0000F9302E0009360000F91123041F489D069 +:1000A0000F9302E0009360000F91123041F493D05F :1000B000109361000F9303E0009360000F911330E1 :1000C000C1F520916200203E51F40F930EE806BF67 :1000D0000F91D89ABA9A2FD0D898BA98F2CF209187 @@ -18,39 +18,47 @@ :1001000051F40F9309E606BF0F91DA9ABA9A13D009 :10011000DA98BA98F2CF20916200203751F40F9309 :1001200000E506BF0F91DB9ABA9A05D0DB98BA9822 -:10013000F2CF88D0AECF2F93DED0DDD0DCD0A9B304 +:10013000F2CF92D0AECF2F931CD11BD11AD1A9B33D :100140009A2FA07F9F70AA27A09362008191981791 -:1001500029F42A2D241739F0439516C07ED03FEF9D -:10016000A2E0AA95AA2E2F91FF27E0E8BA9800EF07 -:100170000BBBCDD0109361000F9302E000936000A1 -:100180000F9141E0A39408952F91089508957A2D39 -:10019000DD27C0E8B0D0652F663430F06C3830F021 -:1001A000683C30F06F3F30F0A1E005C0A2E003C032 -:1001B000A4E001C0A8E0A9937A95703059F7000037 -:1001C0000895E5DF7A2DDD27C0E87030C1F1A991EF -:1001D000A13031F0A23079F0A430C1F0A83009F19B -:1001E0000F930EE806BF0F91D89ABA9A76D0D89896 -:1001F000BA9828D020C00F9307E406BF0F91D99A70 -:10020000BA9A6BD0D998BA981DD015C00F9309E649 -:1002100006BF0F91DA9ABA9A60D0DA98BA9812D0DB -:100220000AC00F9300E506BF0F91DB9ABA9A55D02A -:10023000DB98BA9807D051D07A95703031F607D054 -:100240005AD008957F937FEF76BF7F9108953A50FB -:10025000383208F008953FEF08951F932F933F938E -:100260004F93F8944BB30F9301EF0BBB0F9143D017 -:1002700011E033E020EF110F210F2BBB3CD03A955A -:10028000C9F70F9308EF0BBB0F9135D018E033E09F -:1002900020EF1695210F2BBB2ED03A95C9F77894F5 -:1002A0004BBB4F913F912F911F91089500E10BBFE0 -:1002B00000EF02BB00270895BA9802E400BF0FEFD9 -:1002C00006BF02E003BF01E009BF08950FE00ABBCB -:1002D00002950BBBBA9AC29808952F934F932FEFB4 -:1002E000432F00002A95E9F700004A95D1F7000056 -:1002F0004F912F9108952F933F9321E43FEE3A952C -:10030000F1F72A95E1F700003F912F9108958F931F -:100310009F9324E683EC99E00197F1F72A95D1F7B2 -:1003200024E69F918F9108954D656D6F7279206CD1 -:1003300065642067616D652E205772697474656EFF -:1003400020627920536572676579205961726B6FFD -:0C035000762032372E30392E3230323118 +:1001500029F42A2D241751F0439510C02F9187D0F0 +:100160003FEFA2E0AA95AA2E0CD008952F9100EFA0 +:100170000BBBBA98FED0A4D004D008952F91089557 +:100180000895FF27E0E8BA9800EF0BBBFED010936C +:1001900061000F9302E0009360000F9141E0A3948F +:1001A00008957A2DDD27C0E8E4D0652F663430F05D +:1001B0006C3830F0683C30F06F3F30F0A1E005C0A3 +:1001C000A2E003C0A4E001C0A8E0A9937A95703032 +:1001D00059F700000895E5DF7A2DDD27C0E870307B +:1001E000C1F1A991A13031F0A23079F0A430C1F071 +:1001F000A83009F10F930EE806BF0F91D89ABA9A6A +:100200009FD0D898BA9828D020C00F9307E406BF93 +:100210000F91D99ABA9A94D0D998BA981DD015C08E +:100220000F9309E606BF0F91DA9ABA9A89D0DA9845 +:10023000BA9812D00AC00F9300E506BF0F91DB9A5F +:10024000BA9A7ED0DB98BA9807D07AD07A95703077 +:1002500031F607D08ED008957F937FEF76BF7F91E0 +:1002600008953A50383208F008953FEF08951F93EB +:100270002F933F934F93F8944BB30F9301EF0BBB26 +:100280000F9177D011E033E020EF110F210F2BBB3E +:1002900070D03A95C9F70F9308EF0BBB0F9169D057 +:1002A00018E033E020EF1695210F2BBB62D03A9572 +:1002B000C9F778944BBB4F913F912F911F910895AF +:1002C0000F930EE806BF0F91D89ABA9A52D051D028 +:1002D000D898BA980F9309E606BF0F91D99ABA9A9F +:1002E00048D047D0D998BA980F9300E506BF0F9130 +:1002F000DA9ABA9A3ED03DD0DA98BA980F9307E4CA +:1003000006BF0F91DB9ABA9A34D033D0DB98BA98F3 +:10031000089500E10BBF00EF02BB00270895BA98D3 +:1003200002E400BF0FEF06BF02E003BF01E009BF18 +:1003300008950FE00ABB02950BBBBA9AC2980895C4 +:100340002F934F932FEF432F00002A95E9F70000DA +:100350004A95D1F700004F912F9108952F933F9325 +:100360002AE139EF3A95F1F72A95E1F73F912F917C +:1003700008952F933F9321E43FEE3A95F1F72A95A4 +:10038000E1F700003F912F9108958F939F9324E60A +:1003900083EC99E00197F1F72A95D1F724E69F9134 +:1003A0008F9108954D656D6F7279206C656420673B +:1003B000616D652E205772697474656E20627920B4 +:1003C000536572676579205961726B6F7620323799 +:0803D0002E30392E323032319B :00000001FF diff --git a/firmware.lss b/firmware.lss index 7503312..1f3b640 100644 --- a/firmware.lss +++ b/firmware.lss @@ -1,5 +1,5 @@ -AVRASM ver. 2.2.7 firmware.asm Wed May 18 00:14:04 2022 +AVRASM ver. 2.2.7 firmware.asm Sun May 22 21:06:03 2022 firmware.asm(13): Including file 'def.inc' firmware.asm(21): warning: Register r26 already defined by the .DEF directive @@ -892,7 +892,7 @@ firmware.asm(73): Including file 'macros.asm' 000017 f431 brne quit ; Do not change button flags unless in POLLING state of mcu 000018 b319 in r17, PINA ; Load current pins status of PINA 000019 7f10 andi r17, 0xf0 ; Get pins status of only buttons -00001a d160 rcall delay_50ms ; Delay for button +00001a d193 rcall delay_20ms ; Delay for button 00001b 9310 0062 sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM 00001d bf2f out SREG, r18 @@ -919,9 +919,9 @@ firmware.asm(73): Including file 'macros.asm' 00002b 9518 reti MCU_Init: ; This function executes once on start the main program -00002c d139 rcall init_ports -00002d d128 rcall init_interrupts -00002e d12d rcall init_buzzer +00002c d16c rcall init_ports +00002d d15b rcall init_interrupts +00002e d160 rcall init_buzzer ; ; Init important registers for game @@ -940,10 +940,10 @@ firmware.asm(73): Including file 'macros.asm' MCU_Delay: 000038 e073 ldi temp_r_b, 3 _init_loop_loading: -000039 d0f3 rcall effect_1 +000039 d0fd rcall effect_1 00003a 957a dec temp_r_b 00003b f7e9 brne _init_loop_loading -00003c d14a rcall delay_1s +00003c d188 rcall delay_1s 00003d 2777 clr temp_r_b 00003e 9508 ret @@ -973,7 +973,7 @@ firmware.asm(73): Including file 'macros.asm' showing: ; Showing state 000055 3012 cpi mcu_state_r, SHOWING_STATE 000056 f441 brne polling -000057 d089 rcall show_sequence ; Generate sequence and save answer to SRAM +000057 d093 rcall show_sequence ; Generate sequence and save answer to SRAM 000058 9310 0061 00005a 930f 00005b e003 @@ -1043,15 +1043,15 @@ firmware.asm(73): Including file 'macros.asm' 000097 98ba cbi BUZZ_DIR, BUZZ_PIN 000098 cff2 rjmp btn_4 default: -000099 d088 rcall OCR0A_reset +000099 d092 rcall OCR0A_reset 00009a cfae rjmp loop btn_handler: ; Check the input value with answer in SRAM 00009b 932f push r18 -00009c d0de rcall delay_50ms -00009d d0dd rcall delay_50ms -00009e d0dc rcall delay_50ms +00009c d11c rcall delay_50ms +00009d d11b rcall delay_50ms +00009e d11a rcall delay_50ms 00009f b3a9 in temp_r_c, PINA 0000a0 2f9a mov r25, temp_r_c 0000a1 7fa0 andi temp_r_c, 0xf0 @@ -1065,348 +1065,421 @@ firmware.asm(73): Including file 'macros.asm' 0000a9 2d2a mov r18, seq_length_r 0000aa 1724 cp r18, poll_step_r -0000ab f039 breq _btn_handler_exit_state +0000ab f051 breq _btn_handler_exit_state 0000ac 9543 inc poll_step_r - -0000ad c016 rjmp _btn_handler_exit + +0000ad c010 rjmp _btn_handler_exit _game_over: -0000ae d07e rcall effect_1 -0000af ef3f ldi delay_counter_r, 0xff -0000b0 e0a2 ldi temp_r_c, SEQ_LENGTH -0000b1 95aa dec temp_r_c -0000b2 2eaa mov seq_length_r, temp_r_c +0000ae 912f pop r18 +0000af d087 rcall effect_1 +0000b0 ef3f ldi delay_counter_r, 0xff +0000b1 e0a2 ldi temp_r_c, SEQ_LENGTH +0000b2 95aa dec temp_r_c +0000b3 2eaa mov seq_length_r, temp_r_c +0000b4 d00c rcall reset_game +0000b5 9508 ret _btn_handler_exit_state: -0000b3 912f pop r18 -0000b4 27ff clr ZH -0000b5 e8e0 ldi ZL, $80 -0000b6 98ba cbi BUZZ_DIR, BUZZ_PIN -0000b7 ef00 ldi temp_r, 0xf0 -0000b8 bb0b out LED_PORT, temp_r -0000b9 d0cd rcall delay_1s -0000ba 9310 0061 -0000bc 930f -0000bd e002 -0000be 9300 0060 -0000c0 910f set_state SHOWING_STATE -0000c1 e041 ldi poll_step_r, 1 -0000c2 94a3 inc seq_length_r -0000c3 9508 ret +0000b6 912f pop r18 +0000b7 ef00 ldi temp_r, 0xf0 +0000b8 bb0b out LED_PORT, temp_r +0000b9 98ba cbi BUZZ_DIR, BUZZ_PIN +0000ba d0fe rcall delay_50ms +0000bb d0a4 rcall effect_2 +0000bc d004 rcall reset_game +0000bd 9508 ret _btn_handler_exit: -0000c4 912f pop r18 -0000c5 9508 ret -0000c6 9508 ret +0000be 912f pop r18 +0000bf 9508 ret +0000c0 9508 ret + + reset_game: +0000c1 27ff clr ZH +0000c2 e8e0 ldi ZL, $80 +0000c3 98ba cbi BUZZ_DIR, BUZZ_PIN +0000c4 ef00 ldi temp_r, 0xf0 +0000c5 bb0b out LED_PORT, temp_r +0000c6 d0fe rcall delay_1s +0000c7 9310 0061 +0000c9 930f +0000ca e002 +0000cb 9300 0060 +0000cd 910f set_state SHOWING_STATE +0000ce e041 ldi poll_step_r, 1 +0000cf 94a3 inc seq_length_r +0000d0 9508 ret gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM -0000c7 2d7a mov temp_r_b, seq_length_r -0000c8 27dd clr YH -0000c9 e8c0 ldi YL, $80 +0000d1 2d7a mov temp_r_b, seq_length_r +0000d2 27dd clr YH +0000d3 e8c0 ldi YL, $80 _gen_ran_loop: -0000ca d0b0 rcall delay_50ms ; Delay is required! -0000cb 2f65 mov r22, r21 +0000d4 d0e4 rcall delay_50ms ; Delay is required! +0000d5 2f65 mov r22, r21 -0000cc 3466 cpi r22, 70 -0000cd f030 brlo _gen_answ_1 +0000d6 3466 cpi r22, 70 +0000d7 f030 brlo _gen_answ_1 -0000ce 386c cpi r22, 140 -0000cf f030 brlo _gen_answ_2 +0000d8 386c cpi r22, 140 +0000d9 f030 brlo _gen_answ_2 -0000d0 3c68 cpi r22, 200 -0000d1 f030 brlo _gen_answ_3 +0000da 3c68 cpi r22, 200 +0000db f030 brlo _gen_answ_3 -0000d2 3f6f cpi r22, 255 -0000d3 f030 brlo _gen_answ_4 +0000dc 3f6f cpi r22, 255 +0000dd f030 brlo _gen_answ_4 _gen_answ_1: -0000d4 e0a1 ldi temp_r_c, 0x01 -0000d5 c005 rjmp _gen_ran_write +0000de e0a1 ldi temp_r_c, 0x01 +0000df c005 rjmp _gen_ran_write _gen_answ_2: -0000d6 e0a2 ldi temp_r_c, 0x02 -0000d7 c003 rjmp _gen_ran_write +0000e0 e0a2 ldi temp_r_c, 0x02 +0000e1 c003 rjmp _gen_ran_write _gen_answ_3: -0000d8 e0a4 ldi temp_r_c, 0x04 -0000d9 c001 rjmp _gen_ran_write +0000e2 e0a4 ldi temp_r_c, 0x04 +0000e3 c001 rjmp _gen_ran_write _gen_answ_4: -0000da e0a8 ldi temp_r_c, 0x08 +0000e4 e0a8 ldi temp_r_c, 0x08 _gen_ran_write: -0000db 93a9 st Y+, temp_r_c -0000dc 957a dec temp_r_b -0000dd 3070 cpi temp_r_b, 0 -0000de f759 brne _gen_ran_loop -0000df 0000 nop -0000e0 9508 ret +0000e5 93a9 st Y+, temp_r_c +0000e6 957a dec temp_r_b +0000e7 3070 cpi temp_r_b, 0 +0000e8 f759 brne _gen_ran_loop +0000e9 0000 nop +0000ea 9508 ret show_sequence: -0000e1 dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} +0000eb dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} show_start: -0000e2 2d7a mov temp_r_b, seq_length_r +0000ec 2d7a mov temp_r_b, seq_length_r -0000e3 27dd clr YH -0000e4 e8c0 ldi YL, $80 +0000ed 27dd clr YH +0000ee e8c0 ldi YL, $80 _sequence_loop: -0000e5 3070 cpi temp_r_b, 0 -0000e6 f1c1 breq _seq_quit +0000ef 3070 cpi temp_r_b, 0 +0000f0 f1c1 breq _seq_quit -0000e7 91a9 ld temp_r_c, Y+ -0000e8 30a1 cpi temp_r_c, 0x01 -0000e9 f031 breq beep_1 +0000f1 91a9 ld temp_r_c, Y+ +0000f2 30a1 cpi temp_r_c, 0x01 +0000f3 f031 breq beep_1 -0000ea 30a2 cpi temp_r_c, 0x02 -0000eb f079 breq beep_2 +0000f4 30a2 cpi temp_r_c, 0x02 +0000f5 f079 breq beep_2 -0000ec 30a4 cpi temp_r_c, 0x04 -0000ed f0c1 breq beep_3 +0000f6 30a4 cpi temp_r_c, 0x04 +0000f7 f0c1 breq beep_3 -0000ee 30a8 cpi temp_r_c, 0x08 -0000ef f109 breq beep_4 +0000f8 30a8 cpi temp_r_c, 0x08 +0000f9 f109 breq beep_4 beep_1: -0000f0 930f -0000f1 e80e -0000f2 bf06 -0000f3 910f -0000f4 9ad8 -0000f5 9aba -0000f6 d076 -0000f7 98d8 -0000f8 98ba beep_led_1 -0000f9 d028 rcall OCR0A_reset -0000fa c020 rjmp beep_quit +0000fa 930f +0000fb e80e +0000fc bf06 +0000fd 910f +0000fe 9ad8 +0000ff 9aba +000100 d09f +000101 98d8 +000102 98ba beep_led_1 +000103 d028 rcall OCR0A_reset +000104 c020 rjmp beep_quit beep_2: -0000fb 930f -0000fc e407 -0000fd bf06 -0000fe 910f -0000ff 9ad9 -000100 9aba -000101 d06b -000102 98d9 -000103 98ba beep_led_2 -000104 d01d rcall OCR0A_reset -000105 c015 rjmp beep_quit +000105 930f +000106 e407 +000107 bf06 +000108 910f +000109 9ad9 +00010a 9aba +00010b d094 +00010c 98d9 +00010d 98ba beep_led_2 +00010e d01d rcall OCR0A_reset +00010f c015 rjmp beep_quit beep_3: -000106 930f -000107 e609 -000108 bf06 -000109 910f -00010a 9ada -00010b 9aba -00010c d060 -00010d 98da -00010e 98ba beep_led_3 -00010f d012 rcall OCR0A_reset -000110 c00a rjmp beep_quit +000110 930f +000111 e609 +000112 bf06 +000113 910f +000114 9ada +000115 9aba +000116 d089 +000117 98da +000118 98ba beep_led_3 +000119 d012 rcall OCR0A_reset +00011a c00a rjmp beep_quit beep_4: -000111 930f -000112 e500 -000113 bf06 -000114 910f -000115 9adb -000116 9aba -000117 d055 -000118 98db -000119 98ba beep_led_4 -00011a d007 rcall OCR0A_reset +00011b 930f +00011c e500 +00011d bf06 +00011e 910f +00011f 9adb +000120 9aba +000121 d07e +000122 98db +000123 98ba beep_led_4 +000124 d007 rcall OCR0A_reset beep_quit: -00011b d051 rcall delay -00011c 957a dec temp_r_b -00011d 3070 cpi temp_r_b, 0 -00011e f631 brne _sequence_loop +000125 d07a rcall delay +000126 957a dec temp_r_b +000127 3070 cpi temp_r_b, 0 +000128 f631 brne _sequence_loop _seq_quit: -00011f d007 rcall dec_delay_counter -000120 d05a rcall delay_50ms -000121 9508 ret +000129 d007 rcall dec_delay_counter +00012a d08e rcall delay_50ms +00012b 9508 ret OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt -000122 937f push temp_r_b -000123 ef7f ldi temp_r_b, 0xff -000124 bf76 out OCR0A, temp_r_b -000125 917f pop temp_r_b -000126 9508 ret +00012c 937f push temp_r_b +00012d ef7f ldi temp_r_b, 0xff +00012e bf76 out OCR0A, temp_r_b +00012f 917f pop temp_r_b +000130 9508 ret dec_delay_counter: -000127 503a subi delay_counter_r, 10 -000128 3238 cpi delay_counter_r, 40 -000129 f008 brlo _reset_counter -00012a 9508 ret +000131 503a subi delay_counter_r, 10 +000132 3238 cpi delay_counter_r, 40 +000133 f008 brlo _reset_counter +000134 9508 ret _reset_counter: -00012b ef3f ldi delay_counter_r, 0xff -00012c 9508 ret +000135 ef3f ldi delay_counter_r, 0xff +000136 9508 ret effect_1: ; Shift bits of an leds in port every 50ms -00012d 931f push r17 -00012e 932f push r18 -00012f 933f push r19 -000130 934f push r20 -000131 94f8 cli -000132 b34b in r20, LED_PORT +000137 931f push r17 +000138 932f push r18 +000139 933f push r19 +00013a 934f push r20 +00013b 94f8 cli +00013c b34b in r20, LED_PORT -000133 930f -000134 ef01 -000135 bb0b -000136 910f outi LED_PORT, 0xf1 -000137 d043 rcall delay_50ms -000138 e011 ldi r17, 0x01 -000139 e033 ldi r19, 3 +00013d 930f +00013e ef01 +00013f bb0b +000140 910f outi LED_PORT, 0xf1 +000141 d077 rcall delay_50ms +000142 e011 ldi r17, 0x01 +000143 e033 ldi r19, 3 _eff_1_shift_l: ; Shift bits to left loop -00013a ef20 ldi r18, 0xf0 -00013b 0f11 lsl r17 -00013c 0f21 add r18, r17 -00013d bb2b out LED_PORT, r18 -00013e d03c rcall delay_50ms -00013f 953a dec r19 -000140 f7c9 brne _eff_1_shift_l +000144 ef20 ldi r18, 0xf0 +000145 0f11 lsl r17 +000146 0f21 add r18, r17 +000147 bb2b out LED_PORT, r18 +000148 d070 rcall delay_50ms +000149 953a dec r19 +00014a f7c9 brne _eff_1_shift_l -000141 930f -000142 ef08 -000143 bb0b -000144 910f outi LED_PORT, 0xf8 -000145 d035 rcall delay_50ms -000146 e018 ldi r17, 0x08 -000147 e033 ldi r19, 3 +00014b 930f +00014c ef08 +00014d bb0b +00014e 910f outi LED_PORT, 0xf8 +00014f d069 rcall delay_50ms +000150 e018 ldi r17, 0x08 +000151 e033 ldi r19, 3 _eff_1_shift_r: ; Shift bits to right loop -000148 ef20 ldi r18, 0xf0 -000149 9516 lsr r17 -00014a 0f21 add r18, r17 -00014b bb2b out LED_PORT, r18 -00014c d02e rcall delay_50ms -00014d 953a dec r19 -00014e f7c9 brne _eff_1_shift_r +000152 ef20 ldi r18, 0xf0 +000153 9516 lsr r17 +000154 0f21 add r18, r17 +000155 bb2b out LED_PORT, r18 +000156 d062 rcall delay_50ms +000157 953a dec r19 +000158 f7c9 brne _eff_1_shift_r -00014f 9478 sei +000159 9478 sei ; Out saved PORT values -000150 bb4b out LED_PORT, r20 -000151 914f pop r20 -000152 913f pop r19 -000153 912f pop r18 -000154 911f pop r17 -000155 9508 ret +00015a bb4b out LED_PORT, r20 +00015b 914f pop r20 +00015c 913f pop r19 +00015d 912f pop r18 +00015e 911f pop r17 +00015f 9508 ret + + effect_2: +000160 930f +000161 e80e +000162 bf06 +000163 910f outi OCR0A, 142 +000164 9ad8 sbi LED_PORT, 0 +000165 9aba sbi BUZZ_DIR, BUZZ_PIN +000166 d052 rcall delay_50ms +000167 d051 rcall delay_50ms +000168 98d8 cbi LED_PORT, 0 +000169 98ba cbi BUZZ_DIR, BUZZ_PIN + +00016a 930f +00016b e609 +00016c bf06 +00016d 910f outi OCR0A, 105 +00016e 9ad9 sbi LED_PORT, 1 +00016f 9aba sbi BUZZ_DIR, BUZZ_PIN +000170 d048 rcall delay_50ms +000171 d047 rcall delay_50ms +000172 98d9 cbi LED_PORT, 1 +000173 98ba cbi BUZZ_DIR, BUZZ_PIN + +000174 930f +000175 e500 +000176 bf06 +000177 910f outi OCR0A, 80 +000178 9ada sbi LED_PORT, 2 +000179 9aba sbi BUZZ_DIR, BUZZ_PIN +00017a d03e rcall delay_50ms +00017b d03d rcall delay_50ms +00017c 98da cbi LED_PORT, 2 +00017d 98ba cbi BUZZ_DIR, BUZZ_PIN + +00017e 930f +00017f e407 +000180 bf06 +000181 910f outi OCR0A, 71 +000182 9adb sbi LED_PORT, 3 +000183 9aba sbi BUZZ_DIR, BUZZ_PIN +000184 d034 rcall delay_50ms +000185 d033 rcall delay_50ms +000186 98db cbi LED_PORT, 3 +000187 98ba cbi BUZZ_DIR, BUZZ_PIN +000188 9508 ret init_interrupts: ; ; Enable Port Change Interrupt -000156 e100 ldi temp_r, (1<