bubble/attiny24a_memory-led-game
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feat: answer checking

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This commit is contained in:
Sergey Yarkov 2022-05-03 17:18:31 +03:00
parent 3329131aa2
commit a6d2582379
3 changed files with 536 additions and 409 deletions
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102
firmware.asm
View File

@ -20,6 +20,7 @@
.def temp_r_c = r26 ; Temp general register C .def temp_r_c = r26 ; Temp general register C
.def mcu_state_r = r17 ; Current state of MCU. This register will be compared in an main loop .def mcu_state_r = r17 ; Current state of MCU. This register will be compared in an main loop
.def delay_counter_r = r19 ; Register for storing delay counter .def delay_counter_r = r19 ; Register for storing delay counter
.def poll_step_r = r20 ; Current poll step for checking the input with answer
; ;
; LEDS constants ; LEDS constants
@ -149,6 +150,9 @@ MCU_Init: ; This function executes once on start the main program
rcall init_buzzer rcall init_buzzer
ldi delay_counter_r, 0xff ldi delay_counter_r, 0xff
ldi poll_step_r, 1
clr ZH
ldi ZL, $80
;rcall MCU_Delay ; Wait 1 sec before start main program ;rcall MCU_Delay ; Wait 1 sec before start main program
@ -186,60 +190,107 @@ loop: ; Program loop
polling: ; Polling state polling: ; Polling state
cpi mcu_state_r, POLLING_STATE cpi mcu_state_r, POLLING_STATE
brne completion brne completion
led_1: btn_1:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_1 cpi r18, SW_FLAG_1
brne led_off_1 brne btn_2 ; Check next button
led_on_1: led_on_1:
outi OCR0A, 142 outi OCR0A, 142
sbi LED_PORT, 0 sbi LED_PORT, 0
sbi BUZZ_DIR, BUZZ_PIN sbi BUZZ_DIR, BUZZ_PIN
rjmp led_1 rcall btn_handler
led_off_1:
cbi LED_PORT, 0 cbi LED_PORT, 0
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
led_2: rjmp btn_1
btn_2:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_2 cpi r18, SW_FLAG_2
brne led_off_2 brne btn_3
led_on_2: led_on_2:
outi OCR0A, 71
sbi LED_PORT, 1 sbi LED_PORT, 1
sbi BUZZ_DIR, BUZZ_PIN sbi BUZZ_DIR, BUZZ_PIN
outi OCR0A, 71 rcall btn_handler
rjmp led_2
led_off_2:
cbi LED_PORT, 1 cbi LED_PORT, 1
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
led_3: rjmp btn_2
btn_3:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_3 cpi r18, SW_FLAG_3
brne led_off_3 brne btn_4
led_on_3: led_on_3:
outi OCR0A, 105
sbi LED_PORT, 2 sbi LED_PORT, 2
sbi BUZZ_DIR, BUZZ_PIN sbi BUZZ_DIR, BUZZ_PIN
outi OCR0A, 105 rcall btn_handler
rjmp led_3
led_off_3:
cbi LED_PORT, 2 cbi LED_PORT, 2
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
led_4: rjmp btn_3
btn_4:
lds r18, SW_FLAGS_ADDRESS lds r18, SW_FLAGS_ADDRESS
cpi r18, SW_FLAG_4 cpi r18, SW_FLAG_4
brne led_off_4 brne default
led_on_4: led_on_4:
outi OCR0A, 80
sbi LED_PORT, 3 sbi LED_PORT, 3
sbi BUZZ_DIR, BUZZ_PIN sbi BUZZ_DIR, BUZZ_PIN
outi OCR0A, 80 rcall btn_handler
rjmp led_4
led_off_4:
cbi LED_PORT, 3 cbi LED_PORT, 3
cbi BUZZ_DIR, BUZZ_PIN cbi BUZZ_DIR, BUZZ_PIN
rjmp btn_4
completion: ; Reset delay counter, set MCU state to SHOWING completion: ; Reset delay counter, set MCU state to SHOWING
cpi mcu_state_r, COMPLETION_STATE cpi mcu_state_r, COMPLETION_STATE
brne default brne default
default: ; Do nothing default:
rcall OCR0A_reset
rjmp loop rjmp loop
btn_handler: ; Check the input value with answer in SRAM
push r18
rcall delay_50ms
rcall delay_50ms
rcall delay_50ms
rcall delay_50ms
in temp_r_c, PINA
mov r25, temp_r_c
andi temp_r_c, 0xf0
andi r25, 0x0f
clr temp_r_c
sts SW_FLAGS_ADDRESS, temp_r_c
ld r24, Z+
cp r25, r24 ; Check answer
brne _game_over ; Game over
ldi r18, SEQ_LENGTH
cp r18, poll_step_r
breq _btn_handler_exit_state
inc poll_step_r
rjmp _btn_handler_exit
_game_over:
rcall effect_1
ldi delay_counter_r, 0xff
_btn_handler_exit_state:
pop r18
clr ZH
ldi ZL, $80
cbi BUZZ_DIR, BUZZ_PIN
ldi temp_r, 0xf0
out LED_PORT, temp_r
rcall delay_1s
set_state SHOWING_STATE
ldi poll_step_r, 1
ret
_btn_handler_exit:
pop r18
ret
ret
gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM
ldi temp_r_b, SEQ_LENGTH ldi temp_r_b, SEQ_LENGTH
clr YH clr YH
@ -327,8 +378,7 @@ show_sequence:
_seq_quit: _seq_quit:
rcall dec_delay_counter rcall dec_delay_counter
rcall delay_1s rcall delay_50ms
rjmp show_sequence
ret ret
OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt
@ -348,6 +398,10 @@ dec_delay_counter:
ret ret
effect_1: ; Shift bits of an leds in port every 50ms effect_1: ; Shift bits of an leds in port every 50ms
push r17
push r18
push r19
push r20
in r20, LED_PORT in r20, LED_PORT
outi LED_PORT, 0xf1 outi LED_PORT, 0xf1
@ -379,6 +433,10 @@ effect_1: ; Shift bits of an leds in port every 50ms
; ;
; Out saved PORT values ; Out saved PORT values
out LED_PORT, r20 out LED_PORT, r20
pop r20
pop r19
pop r18
pop r17
ret ret
init_interrupts: init_interrupts:

93
firmware.hex
View File

@ -1,48 +1,55 @@
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:00000001FF :00000001FF

742
firmware.lss
View File

@ -1,11 +1,11 @@
AVRASM ver. 2.2.7 firmware.asm Tue May 03 01:06:34 2022 AVRASM ver. 2.2.7 firmware.asm Tue May 03 17:14:17 2022
firmware.asm(13): Including file 'def.inc' firmware.asm(13): Including file 'def.inc'
firmware.asm(20): warning: Register r26 already defined by the .DEF directive firmware.asm(20): warning: Register r26 already defined by the .DEF directive
firmware.asm(72): Including file 'macros.asm' firmware.asm(73): Including file 'macros.asm'
firmware.asm(13): Including file 'def.inc' firmware.asm(13): Including file 'def.inc'
firmware.asm(72): Including file 'macros.asm' firmware.asm(73): Including file 'macros.asm'
; Project name: memory-led-game ; Project name: memory-led-game
@ -704,6 +704,7 @@ firmware.asm(72): Including file 'macros.asm'
.def temp_r_c = r26 ; Temp general register C .def temp_r_c = r26 ; Temp general register C
.def mcu_state_r = r17 ; Current state of MCU. This register will be compared in an main loop .def mcu_state_r = r17 ; Current state of MCU. This register will be compared in an main loop
.def delay_counter_r = r19 ; Register for storing delay counter .def delay_counter_r = r19 ; Register for storing delay counter
.def poll_step_r = r20 ; Current poll step for checking the input with answer
; ;
; LEDS constants ; LEDS constants
@ -862,7 +863,7 @@ firmware.asm(72): Including file 'macros.asm'
; ;
; Setup vectors ; Setup vectors
000000 c038 rjmp start ; Program start at RESET vector 000000 c03b rjmp start ; Program start at RESET vector
000001 9518 reti ; External Interrupt Request 0 / inactive 000001 9518 reti ; External Interrupt Request 0 / inactive
000002 c00e rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active 000002 c00e rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active
000003 9518 reti ; Pin Change Interrupt Request 1 / inactive 000003 9518 reti ; Pin Change Interrupt Request 1 / inactive
@ -891,7 +892,7 @@ firmware.asm(72): Including file 'macros.asm'
000017 f431 brne quit ; Do not change button flags unless in POLLING state of mcu 000017 f431 brne quit ; Do not change button flags unless in POLLING state of mcu
000018 b319 in r17, PINA ; Load current pins status of PINA 000018 b319 in r17, PINA ; Load current pins status of PINA
000019 7f10 andi r17, 0xf0 ; Get pins status of only buttons 000019 7f10 andi r17, 0xf0 ; Get pins status of only buttons
00001a d122 rcall delay_50ms ; Delay for button 00001a d15a rcall delay_50ms ; Delay for button
00001b 9310 0062 sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM 00001b 9310 0062 sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM
00001d bf2f out SREG, r18 00001d bf2f out SREG, r18
@ -918,424 +919,485 @@ firmware.asm(72): Including file 'macros.asm'
00002b 9518 reti 00002b 9518 reti
MCU_Init: ; This function executes once on start the main program MCU_Init: ; This function executes once on start the main program
00002c d0fb rcall init_ports 00002c d133 rcall init_ports
00002d d0ea rcall init_interrupts 00002d d122 rcall init_interrupts
00002e d0ef rcall init_buzzer 00002e d127 rcall init_buzzer
00002f ef3f ldi delay_counter_r, 0xff 00002f ef3f ldi delay_counter_r, 0xff
000030 e041 ldi poll_step_r, 1
000031 27ff clr ZH
000032 e8e0 ldi ZL, $80
;rcall MCU_Delay ; Wait 1 sec before start main program ;rcall MCU_Delay ; Wait 1 sec before start main program
000030 9478 sei ; Enable Global Interrupts 000033 9478 sei ; Enable Global Interrupts
000031 9508 ret 000034 9508 ret
MCU_Delay: MCU_Delay:
000032 e006 ldi temp_r, 6 000035 e006 ldi temp_r, 6
_init_loop_loading: _init_loop_loading:
000033 d0c5 rcall effect_1 000036 d0f2 rcall effect_1
000034 950a dec temp_r 000037 950a dec temp_r
000035 f7e9 brne _init_loop_loading 000038 f7e9 brne _init_loop_loading
000036 d112 rcall delay_1s 000039 d147 rcall delay_1s
000037 2700 clr temp_r 00003a 2700 clr temp_r
000038 9508 ret 00003b 9508 ret
; ;
; Program start at reset ; Program start at reset
start: start:
000039 ed0f 00003c ed0f
00003a bf0d 00003d bf0d
00003b 2700 init_stack_p temp_r, RAMEND 00003e 2700 init_stack_p temp_r, RAMEND
00003c 9310 0061 00003f 9310 0061
00003e 930f 000041 930f
00003f e001 000042 e001
000040 9300 0060 000043 9300 0060
000042 910f set_state INIT_STATE 000045 910f set_state INIT_STATE
loop: ; Program loop loop: ; Program loop
000043 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS 000046 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS
init: ; Init state init: ; Init state
000045 3011 cpi mcu_state_r, INIT_STATE 000048 3011 cpi mcu_state_r, INIT_STATE
000046 f441 brne showing 000049 f441 brne showing
000047 dfe4 rcall MCU_Init 00004a dfe1 rcall MCU_Init
000048 9310 0061 00004b 9310 0061
00004a 930f 00004d 930f
00004b e002 00004e e002
00004c 9300 0060 00004f 9300 0060
00004e 910f set_state SHOWING_STATE 000051 910f set_state SHOWING_STATE
showing: ; Showing state showing: ; Showing state
00004f 3012 cpi mcu_state_r, SHOWING_STATE 000052 3012 cpi mcu_state_r, SHOWING_STATE
000050 f441 brne polling 000053 f441 brne polling
000051 d05a rcall show_sequence ; Generate sequence and save answer to SRAM 000054 d088 rcall show_sequence ; Generate sequence and save answer to SRAM
000052 9310 0061 000055 9310 0061
000054 930f 000057 930f
000055 e003 000058 e003
000056 9300 0060 000059 9300 0060
000058 910f set_state POLLING_STATE 00005b 910f set_state POLLING_STATE
polling: ; Polling state polling: ; Polling state
000059 3013 cpi mcu_state_r, POLLING_STATE 00005c 3013 cpi mcu_state_r, POLLING_STATE
00005a f5a1 brne completion 00005d f5c1 brne completion
led_1: btn_1:
00005b 9120 0062 lds r18, SW_FLAGS_ADDRESS 00005e 9120 0062 lds r18, SW_FLAGS_ADDRESS
00005d 3e20 cpi r18, SW_FLAG_1 000060 3e20 cpi r18, SW_FLAG_1
00005e f439 brne led_off_1 000061 f451 brne btn_2 ; Check next button
led_on_1: led_on_1:
00005f 930f 000062 930f
000060 e80e 000063 e80e
000061 bf06 000064 bf06
000062 910f outi OCR0A, 142 000065 910f outi OCR0A, 142
000063 9ad8 sbi LED_PORT, 0 000066 9ad8 sbi LED_PORT, 0
000064 9aba sbi BUZZ_DIR, BUZZ_PIN 000067 9aba sbi BUZZ_DIR, BUZZ_PIN
000065 cff5 rjmp led_1 000068 d031 rcall btn_handler
led_off_1: 000069 98d8 cbi LED_PORT, 0
000066 98d8 cbi LED_PORT, 0 00006a 98ba cbi BUZZ_DIR, BUZZ_PIN
000067 98ba cbi BUZZ_DIR, BUZZ_PIN 00006b cff2 rjmp btn_1
led_2: btn_2:
000068 9120 0062 lds r18, SW_FLAGS_ADDRESS 00006c 9120 0062 lds r18, SW_FLAGS_ADDRESS
00006a 3d20 cpi r18, SW_FLAG_2 00006e 3d20 cpi r18, SW_FLAG_2
00006b f439 brne led_off_2 00006f f451 brne btn_3
led_on_2: led_on_2:
00006c 9ad9 sbi LED_PORT, 1 000070 930f
00006d 9aba sbi BUZZ_DIR, BUZZ_PIN 000071 e407
00006e 930f 000072 bf06
00006f e407 000073 910f outi OCR0A, 71
000070 bf06 000074 9ad9 sbi LED_PORT, 1
000071 910f outi OCR0A, 71 000075 9aba sbi BUZZ_DIR, BUZZ_PIN
000072 cff5 rjmp led_2 000076 d023 rcall btn_handler
led_off_2: 000077 98d9 cbi LED_PORT, 1
000073 98d9 cbi LED_PORT, 1 000078 98ba cbi BUZZ_DIR, BUZZ_PIN
000074 98ba cbi BUZZ_DIR, BUZZ_PIN 000079 cff2 rjmp btn_2
led_3: btn_3:
000075 9120 0062 lds r18, SW_FLAGS_ADDRESS 00007a 9120 0062 lds r18, SW_FLAGS_ADDRESS
000077 3b20 cpi r18, SW_FLAG_3 00007c 3b20 cpi r18, SW_FLAG_3
000078 f439 brne led_off_3 00007d f451 brne btn_4
led_on_3: led_on_3:
000079 9ada sbi LED_PORT, 2 00007e 930f
00007a 9aba sbi BUZZ_DIR, BUZZ_PIN 00007f e609
00007b 930f 000080 bf06
00007c e609 000081 910f outi OCR0A, 105
00007d bf06 000082 9ada sbi LED_PORT, 2
00007e 910f outi OCR0A, 105 000083 9aba sbi BUZZ_DIR, BUZZ_PIN
00007f cff5 rjmp led_3 000084 d015 rcall btn_handler
led_off_3: 000085 98da cbi LED_PORT, 2
000080 98da cbi LED_PORT, 2 000086 98ba cbi BUZZ_DIR, BUZZ_PIN
000081 98ba cbi BUZZ_DIR, BUZZ_PIN 000087 cff2 rjmp btn_3
led_4: btn_4:
000082 9120 0062 lds r18, SW_FLAGS_ADDRESS 000088 9120 0062 lds r18, SW_FLAGS_ADDRESS
000084 3720 cpi r18, SW_FLAG_4 00008a 3720 cpi r18, SW_FLAG_4
000085 f439 brne led_off_4 00008b f461 brne default
led_on_4: led_on_4:
000086 9adb sbi LED_PORT, 3 00008c 930f
000087 9aba sbi BUZZ_DIR, BUZZ_PIN 00008d e500
000088 930f 00008e bf06
000089 e500 00008f 910f outi OCR0A, 80
00008a bf06 000090 9adb sbi LED_PORT, 3
00008b 910f outi OCR0A, 80 000091 9aba sbi BUZZ_DIR, BUZZ_PIN
00008c cff5 rjmp led_4 000092 d007 rcall btn_handler
led_off_4: 000093 98db cbi LED_PORT, 3
00008d 98db cbi LED_PORT, 3 000094 98ba cbi BUZZ_DIR, BUZZ_PIN
00008e 98ba cbi BUZZ_DIR, BUZZ_PIN 000095 cff2 rjmp btn_4
completion: ; Reset delay counter, set MCU state to SHOWING completion: ; Reset delay counter, set MCU state to SHOWING
00008f 3014 cpi mcu_state_r, COMPLETION_STATE 000096 3014 cpi mcu_state_r, COMPLETION_STATE
000090 f401 brne default 000097 f401 brne default
default: ; Do nothing default:
000091 cfb1 rjmp loop 000098 d085 rcall OCR0A_reset
000099 cfac rjmp loop
btn_handler: ; Check the input value with answer in SRAM
00009a 932f push r18
00009b d0d9 rcall delay_50ms
00009c d0d8 rcall delay_50ms
00009d d0d7 rcall delay_50ms
00009e d0d6 rcall delay_50ms
00009f b3a9 in temp_r_c, PINA
0000a0 2f9a mov r25, temp_r_c
0000a1 7fa0 andi temp_r_c, 0xf0
0000a2 709f andi r25, 0x0f
0000a3 27aa clr temp_r_c
0000a4 93a0 0062 sts SW_FLAGS_ADDRESS, temp_r_c
0000a6 9181 ld r24, Z+
0000a7 1798 cp r25, r24 ; Check answer
0000a8 f429 brne _game_over ; Game over
0000a9 e024 ldi r18, SEQ_LENGTH
0000aa 1724 cp r18, poll_step_r
0000ab f021 breq _btn_handler_exit_state
0000ac 9543 inc poll_step_r
0000ad c012 rjmp _btn_handler_exit
_game_over:
0000ae d07a rcall effect_1
0000af ef3f ldi delay_counter_r, 0xff
_btn_handler_exit_state:
0000b0 912f pop r18
0000b1 27ff clr ZH
0000b2 e8e0 ldi ZL, $80
0000b3 98ba cbi BUZZ_DIR, BUZZ_PIN
0000b4 ef00 ldi temp_r, 0xf0
0000b5 bb0b out LED_PORT, temp_r
0000b6 d0ca rcall delay_1s
0000b7 9310 0061
0000b9 930f
0000ba e002
0000bb 9300 0060
0000bd 910f set_state SHOWING_STATE
0000be e041 ldi poll_step_r, 1
0000bf 9508 ret
_btn_handler_exit:
0000c0 912f pop r18
0000c1 9508 ret
0000c2 9508 ret
gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM
000092 e074 ldi temp_r_b, SEQ_LENGTH 0000c3 e074 ldi temp_r_b, SEQ_LENGTH
000093 27dd clr YH 0000c4 27dd clr YH
000094 e8c0 ldi YL, $80 0000c5 e8c0 ldi YL, $80
_gen_ran_loop: _gen_ran_loop:
000095 d0a7 rcall delay_50ms ; Delay is required! 0000c6 d0ae rcall delay_50ms ; Delay is required!
000096 2f65 mov r22, r21 0000c7 2f65 mov r22, r21
000097 3466 cpi r22, 70 0000c8 3466 cpi r22, 70
000098 f030 brlo _gen_answ_1 0000c9 f030 brlo _gen_answ_1
000099 386c cpi r22, 140 0000ca 386c cpi r22, 140
00009a f030 brlo _gen_answ_2 0000cb f030 brlo _gen_answ_2
00009b 3c68 cpi r22, 200 0000cc 3c68 cpi r22, 200
00009c f030 brlo _gen_answ_3 0000cd f030 brlo _gen_answ_3
00009d 3f6f cpi r22, 255 0000ce 3f6f cpi r22, 255
00009e f030 brlo _gen_answ_4 0000cf f030 brlo _gen_answ_4
_gen_answ_1: _gen_answ_1:
00009f e0a1 ldi temp_r_c, 0x01 0000d0 e0a1 ldi temp_r_c, 0x01
0000a0 c005 rjmp _gen_ran_write 0000d1 c005 rjmp _gen_ran_write
_gen_answ_2: _gen_answ_2:
0000a1 e0a2 ldi temp_r_c, 0x02 0000d2 e0a2 ldi temp_r_c, 0x02
0000a2 c003 rjmp _gen_ran_write 0000d3 c003 rjmp _gen_ran_write
_gen_answ_3: _gen_answ_3:
0000a3 e0a4 ldi temp_r_c, 0x04 0000d4 e0a4 ldi temp_r_c, 0x04
0000a4 c001 rjmp _gen_ran_write 0000d5 c001 rjmp _gen_ran_write
_gen_answ_4: _gen_answ_4:
0000a5 e0a8 ldi temp_r_c, 0x08 0000d6 e0a8 ldi temp_r_c, 0x08
_gen_ran_write: _gen_ran_write:
0000a6 93a9 st Y+, temp_r_c 0000d7 93a9 st Y+, temp_r_c
0000a7 957a dec temp_r_b 0000d8 957a dec temp_r_b
0000a8 3070 cpi temp_r_b, 0 0000d9 3070 cpi temp_r_b, 0
0000a9 f759 brne _gen_ran_loop 0000da f759 brne _gen_ran_loop
0000aa 0000 nop 0000db 0000 nop
0000ab 9508 ret 0000dc 9508 ret
show_sequence: show_sequence:
0000ac dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} 0000dd dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH}
show_start: show_start:
0000ad e074 ldi temp_r_b, SEQ_LENGTH 0000de e074 ldi temp_r_b, SEQ_LENGTH
0000ae 27dd clr YH 0000df 27dd clr YH
0000af e8c0 ldi YL, $80 0000e0 e8c0 ldi YL, $80
_sequence_loop: _sequence_loop:
0000b0 3070 cpi temp_r_b, 0 0000e1 3070 cpi temp_r_b, 0
0000b1 f1c1 breq _seq_quit 0000e2 f1c1 breq _seq_quit
0000b2 91a9 ld temp_r_c, Y+ 0000e3 91a9 ld temp_r_c, Y+
0000b3 30a1 cpi temp_r_c, 0x01 0000e4 30a1 cpi temp_r_c, 0x01
0000b4 f031 breq beep_1 0000e5 f031 breq beep_1
0000b5 30a2 cpi temp_r_c, 0x02 0000e6 30a2 cpi temp_r_c, 0x02
0000b6 f079 breq beep_2 0000e7 f079 breq beep_2
0000b7 30a4 cpi temp_r_c, 0x04 0000e8 30a4 cpi temp_r_c, 0x04
0000b8 f0c1 breq beep_3 0000e9 f0c1 breq beep_3
0000b9 30a8 cpi temp_r_c, 0x08 0000ea 30a8 cpi temp_r_c, 0x08
0000ba f109 breq beep_4 0000eb f109 breq beep_4
beep_1: beep_1:
0000bb 930f 0000ec 930f
0000bc e80e 0000ed e80e
0000bd bf06 0000ee bf06
0000be 910f 0000ef 910f
0000bf 9ad8 0000f0 9ad8
0000c0 9aba 0000f1 9aba
0000c1 d06d 0000f2 d074
0000c2 98d8 0000f3 98d8
0000c3 98ba beep_led_1 0000f4 98ba beep_led_1
0000c4 d029 rcall OCR0A_reset 0000f5 d028 rcall OCR0A_reset
0000c5 c020 rjmp beep_quit 0000f6 c020 rjmp beep_quit
beep_2: beep_2:
0000c6 930f 0000f7 930f
0000c7 e407 0000f8 e407
0000c8 bf06 0000f9 bf06
0000c9 910f 0000fa 910f
0000ca 9ad9 0000fb 9ad9
0000cb 9aba 0000fc 9aba
0000cc d062 0000fd d069
0000cd 98d9 0000fe 98d9
0000ce 98ba beep_led_2 0000ff 98ba beep_led_2
0000cf d01e rcall OCR0A_reset 000100 d01d rcall OCR0A_reset
0000d0 c015 rjmp beep_quit 000101 c015 rjmp beep_quit
beep_3: beep_3:
0000d1 930f 000102 930f
0000d2 e609 000103 e609
0000d3 bf06 000104 bf06
0000d4 910f 000105 910f
0000d5 9ada 000106 9ada
0000d6 9aba 000107 9aba
0000d7 d057 000108 d05e
0000d8 98da 000109 98da
0000d9 98ba beep_led_3 00010a 98ba beep_led_3
0000da d013 rcall OCR0A_reset 00010b d012 rcall OCR0A_reset
0000db c00a rjmp beep_quit 00010c c00a rjmp beep_quit
beep_4: beep_4:
0000dc 930f 00010d 930f
0000dd e500 00010e e500
0000de bf06 00010f bf06
0000df 910f 000110 910f
0000e0 9adb 000111 9adb
0000e1 9aba 000112 9aba
0000e2 d04c 000113 d053
0000e3 98db 000114 98db
0000e4 98ba beep_led_4 000115 98ba beep_led_4
0000e5 d008 rcall OCR0A_reset 000116 d007 rcall OCR0A_reset
beep_quit: beep_quit:
0000e6 d048 rcall delay 000117 d04f rcall delay
0000e7 957a dec temp_r_b 000118 957a dec temp_r_b
0000e8 3070 cpi temp_r_b, 0 000119 3070 cpi temp_r_b, 0
0000e9 f631 brne _sequence_loop 00011a f631 brne _sequence_loop
_seq_quit: _seq_quit:
0000ea d008 rcall dec_delay_counter 00011b d007 rcall dec_delay_counter
0000eb d05d rcall delay_1s 00011c d058 rcall delay_50ms
0000ec cfbf rjmp show_sequence 00011d 9508 ret
0000ed 9508 ret
OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt
0000ee 937f push temp_r_b 00011e 937f push temp_r_b
0000ef ef7f ldi temp_r_b, 0xff 00011f ef7f ldi temp_r_b, 0xff
0000f0 bf76 out OCR0A, temp_r_b 000120 bf76 out OCR0A, temp_r_b
0000f1 917f pop temp_r_b 000121 917f pop temp_r_b
0000f2 9508 ret 000122 9508 ret
dec_delay_counter: dec_delay_counter:
0000f3 503a subi delay_counter_r, 10 000123 503a subi delay_counter_r, 10
0000f4 3238 cpi delay_counter_r, 40 000124 3238 cpi delay_counter_r, 40
0000f5 f008 brlo _reset_counter 000125 f008 brlo _reset_counter
0000f6 9508 ret 000126 9508 ret
_reset_counter: _reset_counter:
0000f7 ef3f ldi delay_counter_r, 0xff 000127 ef3f ldi delay_counter_r, 0xff
0000f8 9508 ret 000128 9508 ret
effect_1: ; Shift bits of an leds in port every 50ms effect_1: ; Shift bits of an leds in port every 50ms
0000f9 b34b in r20, LED_PORT 000129 931f push r17
00012a 932f push r18
00012b 933f push r19
00012c 934f push r20
00012d b34b in r20, LED_PORT
0000fa 930f 00012e 930f
0000fb ef01 00012f ef01
0000fc bb0b 000130 bb0b
0000fd 910f outi LED_PORT, 0xf1 000131 910f outi LED_PORT, 0xf1
0000fe d03e rcall delay_50ms 000132 d042 rcall delay_50ms
0000ff e011 ldi r17, 0x01 000133 e011 ldi r17, 0x01
000100 e033 ldi r19, 3 000134 e033 ldi r19, 3
_eff_1_shift_l: ; Shift bits to left loop _eff_1_shift_l: ; Shift bits to left loop
000101 ef20 ldi r18, 0xf0 000135 ef20 ldi r18, 0xf0
000102 0f11 lsl r17 000136 0f11 lsl r17
000103 0f21 add r18, r17 000137 0f21 add r18, r17
000104 bb2b out LED_PORT, r18 000138 bb2b out LED_PORT, r18
000105 d037 rcall delay_50ms 000139 d03b rcall delay_50ms
000106 953a dec r19 00013a 953a dec r19
000107 f7c9 brne _eff_1_shift_l 00013b f7c9 brne _eff_1_shift_l
000108 930f 00013c 930f
000109 ef08 00013d ef08
00010a bb0b 00013e bb0b
00010b 910f outi LED_PORT, 0xf8 00013f 910f outi LED_PORT, 0xf8
00010c d030 rcall delay_50ms 000140 d034 rcall delay_50ms
00010d e018 ldi r17, 0x08 000141 e018 ldi r17, 0x08
00010e e033 ldi r19, 3 000142 e033 ldi r19, 3
_eff_1_shift_r: ; Shift bits to right loop _eff_1_shift_r: ; Shift bits to right loop
00010f ef20 ldi r18, 0xf0 000143 ef20 ldi r18, 0xf0
000110 9516 lsr r17 000144 9516 lsr r17
000111 0f21 add r18, r17 000145 0f21 add r18, r17
000112 bb2b out LED_PORT, r18 000146 bb2b out LED_PORT, r18
000113 d029 rcall delay_50ms 000147 d02d rcall delay_50ms
000114 953a dec r19 000148 953a dec r19
000115 f7c9 brne _eff_1_shift_r 000149 f7c9 brne _eff_1_shift_r
; ;
; Out saved PORT values ; Out saved PORT values
000116 bb4b out LED_PORT, r20 00014a bb4b out LED_PORT, r20
000117 9508 ret 00014b 914f pop r20
00014c 913f pop r19
00014d 912f pop r18
00014e 911f pop r17
00014f 9508 ret
init_interrupts: init_interrupts:
; ;
; Enable Port Change Interrupt ; Enable Port Change Interrupt
000118 e100 ldi temp_r, (1<<PCIE0) 000150 e100 ldi temp_r, (1<<PCIE0)
000119 bf0b out GIMSK, temp_r 000151 bf0b out GIMSK, temp_r
; ;
; Set Pin Change Mask Register ; Set Pin Change Mask Register
00011a ef00 ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7) 000152 ef00 ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7)
00011b bb02 out PCMSK0, temp_r 000153 bb02 out PCMSK0, temp_r
00011c 2700 clr temp_r 000154 2700 clr temp_r
00011d 9508 ret 000155 9508 ret
init_buzzer: init_buzzer:
00011e 98ba cbi BUZZ_DIR, BUZZ_PIN 000156 98ba cbi BUZZ_DIR, BUZZ_PIN
; Setup timer ; Setup timer
00011f e402 ldi temp_r, (1<<COM0A0) | (1<<WGM01) ; Set CTC timer mode and toggle OC0A pin on Compare Match 000157 e402 ldi temp_r, (1<<COM0A0) | (1<<WGM01) ; Set CTC timer mode and toggle OC0A pin on Compare Match
000120 bf00 out TCCR0A, temp_r 000158 bf00 out TCCR0A, temp_r
000121 ef0f ldi temp_r, 255 000159 ef0f ldi temp_r, 255
000122 bf06 out OCR0A, temp_r 00015a bf06 out OCR0A, temp_r
000123 e002 ldi temp_r, (1<<CS01) ; Prescale on 8 00015b e002 ldi temp_r, (1<<CS01) ; Prescale on 8
000124 bf03 out TCCR0B, temp_r 00015c bf03 out TCCR0B, temp_r
000125 e001 ldi temp_r, (1<<TOIE0) ; Enable Timer/Counter0 Overflow Interrupt 00015d e001 ldi temp_r, (1<<TOIE0) ; Enable Timer/Counter0 Overflow Interrupt
000126 bf09 out TIMSK0, temp_r 00015e bf09 out TIMSK0, temp_r
000127 9508 ret 00015f 9508 ret
init_ports: ; Init MCU ports init_ports: ; Init MCU ports
000128 e00f ldi temp_r, 0x0f ; Setup PORTA 000160 e00f ldi temp_r, 0x0f ; Setup PORTA
000129 bb0a out DDRA, temp_r ; Set directions of leds and buttons 000161 bb0a out DDRA, temp_r ; Set directions of leds and buttons
00012a 9502 swap temp_r 000162 9502 swap temp_r
00012b bb0b out PORTA, temp_r ; Set low signal on leds and pull-up on buttons 000163 bb0b out PORTA, temp_r ; Set low signal on leds and pull-up on buttons
; Setup PORTB ; Setup PORTB
00012c 9aba sbi DDRB, BUZZ_PIN ; Set direction of buzzer pin to output 000164 9aba sbi DDRB, BUZZ_PIN ; Set direction of buzzer pin to output
00012d 98c2 cbi PORTB, BUZZ_PIN ; Set low signal on buzzer 000165 98c2 cbi PORTB, BUZZ_PIN ; Set low signal on buzzer
00012e 9508 ret 000166 9508 ret
delay: ; For 1MHz frequency delay: ; For 1MHz frequency
00012f 932f push r18 000167 932f push r18
000130 934f push r20 000168 934f push r20
000131 ef2f ldi r18, 255 000169 ef2f ldi r18, 255
000132 2f43 mov r20, delay_counter_r 00016a 2f43 mov r20, delay_counter_r
_delay_loop: _delay_loop:
000133 0000 nop 00016b 0000 nop
000134 952a dec r18 00016c 952a dec r18
000135 f7e9 brne _delay_loop 00016d f7e9 brne _delay_loop
000136 0000 nop 00016e 0000 nop
000137 954a dec r20 00016f 954a dec r20
000138 f7d1 brne _delay_loop 000170 f7d1 brne _delay_loop
000139 0000 nop 000171 0000 nop
00013a 914f pop r20 000172 914f pop r20
00013b 912f pop r18 000173 912f pop r18
00013c 9508 ret 000174 9508 ret
delay_50ms: ; For 1MHz frequency delay_50ms: ; For 1MHz frequency
00013d 932f push r18 000175 932f push r18
00013e 933f push r19 000176 933f push r19
00013f e421 ldi r18, 65 000177 e421 ldi r18, 65
000140 ee3f ldi r19, 239 000178 ee3f ldi r19, 239
_loop_d_50ms: _loop_d_50ms:
000141 953a dec r19 000179 953a dec r19
000142 f7f1 brne _loop_d_50ms 00017a f7f1 brne _loop_d_50ms
000143 952a dec r18 00017b 952a dec r18
000144 f7e1 brne _loop_d_50ms 00017c f7e1 brne _loop_d_50ms
000145 0000 nop 00017d 0000 nop
000146 913f pop r19 00017e 913f pop r19
000147 912f pop r18 00017f 912f pop r18
000148 9508 ret 000180 9508 ret
delay_1s: ; For 1MHz frequency delay_1s: ; For 1MHz frequency
.equ outer_count = 100 .equ outer_count = 100
.equ inner_count = 2499 .equ inner_count = 2499
000149 e624 ldi r18, outer_count 000181 e624 ldi r18, outer_count
_reset: _reset:
00014a ec83 ldi r24, low(inner_count) 000182 ec83 ldi r24, low(inner_count)
00014b e099 ldi r25, high(inner_count) 000183 e099 ldi r25, high(inner_count)
_loop: _loop:
00014c 9701 sbiw r24, 1 000184 9701 sbiw r24, 1
00014d f7f1 brne _loop 000185 f7f1 brne _loop
00014e 952a dec r18 000186 952a dec r18
00014f f7d1 brne _reset 000187 f7d1 brne _reset
000150 e624 ldi r18, outer_count 000188 e624 ldi r18, outer_count
000151 9508 ret 000189 9508 ret
000152 654d 00018a 654d
000153 6f6d 00018b 6f6d
000154 7972 00018c 7972
000155 6c20 00018d 6c20
000156 6465 00018e 6465
000157 6720 00018f 6720
000158 6d61 000190 6d61
000159 2e65 000191 2e65
00015a 5720 000192 5720
00015b 6972 000193 6972
00015c 7474 000194 7474
00015d 6e65 000195 6e65
00015e 6220 000196 6220
00015f 2079 000197 2079
000160 6553 000198 6553
000161 6772 000199 6772
000162 7965 00019a 7965
000163 5920 00019b 5920
000164 7261 00019c 7261
000165 6f6b 00019d 6f6b
000166 2076 00019e 2076
000167 3732 00019f 3732
000168 302e 0001a0 302e
000169 2e39 0001a1 2e39
00016a 3032 0001a2 3032
RESOURCE USE INFORMATION RESOURCE USE INFORMATION
@ -1353,38 +1415,38 @@ counted separately from r26..r31 here.
.dseg memory usage only counts static data declared with .byte .dseg memory usage only counts static data declared with .byte
"ATtiny24A" register use summary: "ATtiny24A" register use summary:
x : 0 y : 2 z : 0 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0 x : 0 y : 2 z : 1 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 0 r11: 0 r12: 0 r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 0 r11: 0 r12: 0
r13: 0 r14: 0 r15: 0 r16: 79 r17: 21 r18: 29 r19: 13 r20: 6 r13: 0 r14: 0 r15: 0 r16: 85 r17: 24 r18: 36 r19: 16 r20: 12
r21: 4 r22: 5 r23: 15 r24: 2 r25: 1 r26: 10 r27: 0 r28: 2 r21: 4 r22: 5 r23: 15 r24: 4 r25: 4 r26: 15 r27: 0 r28: 2
r29: 2 r30: 0 r31: 0 r29: 2 r30: 2 r31: 2
Registers used: 14 out of 35 (40.0%) Registers used: 17 out of 35 (48.6%)
"ATtiny24A" instruction use summary: "ATtiny24A" instruction use summary:
.lds : 0 .sts : 0 adc : 0 add : 3 adiw : 0 and : 0 .lds : 0 .sts : 0 adc : 0 add : 3 adiw : 0 and : 0
andi : 1 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0 andi : 3 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
brcc : 0 brcs : 0 break : 0 breq : 5 brge : 0 brhc : 0 brcc : 0 brcs : 0 break : 0 breq : 6 brge : 0 brhc : 0
brhs : 0 brid : 0 brie : 0 brlo : 5 brlt : 0 brmi : 0 brhs : 0 brid : 0 brie : 0 brlo : 5 brlt : 0 brmi : 0
brne : 20 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0 brne : 21 brpl : 0 brsh : 0 brtc : 0 brts : 0 brvc : 0
brvs : 0 bset : 0 bst : 0 cbi : 18 cbr : 0 clc : 0 brvs : 0 bset : 0 bst : 0 cbi : 19 cbr : 0 clc : 0
clh : 0 cli : 0 cln : 0 clr : 5 cls : 0 clt : 0 clh : 0 cli : 0 cln : 0 clr : 8 cls : 0 clt : 0
clv : 0 clz : 0 com : 0 cp : 0 cpc : 0 cpi : 21 clv : 0 clz : 0 com : 0 cp : 2 cpc : 0 cpi : 21
cpse : 0 dec : 10 eor : 1 icall : 0 ijmp : 0 in : 5 cpse : 0 dec : 10 eor : 1 icall : 0 ijmp : 0 in : 6
inc : 0 ld : 1 ldd : 0 ldi : 47 lds : 6 lpm : 0 inc : 1 ld : 2 ldd : 0 ldi : 55 lds : 6 lpm : 0
lsl : 1 lsr : 1 mov : 2 movw : 0 neg : 0 nop : 5 lsl : 1 lsr : 1 mov : 3 movw : 0 neg : 0 nop : 5
or : 0 ori : 0 out : 25 pop : 21 push : 21 rcall : 25 or : 0 ori : 0 out : 26 pop : 28 push : 27 rcall : 36
ret : 14 reti : 16 rjmp : 16 rol : 0 ror : 0 sbc : 0 ret : 17 reti : 16 rjmp : 16 rol : 0 ror : 0 sbc : 0
sbci : 0 sbi : 17 sbic : 0 sbis : 0 sbiw : 1 sbr : 0 sbci : 0 sbi : 17 sbic : 0 sbis : 0 sbiw : 1 sbr : 0
sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 1 sen : 0 sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 1 sen : 0
ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 0 ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 0
spm : 0 st : 1 std : 0 sts : 7 sub : 0 subi : 1 spm : 0 st : 1 std : 0 sts : 10 sub : 0 subi : 1
swap : 2 tst : 0 wdr : 0 swap : 2 tst : 0 wdr : 0
Instructions used: 32 out of 105 (30.5%) Instructions used: 34 out of 105 (32.4%)
"ATtiny24A" memory use summary [bytes]: "ATtiny24A" memory use summary [bytes]:
Segment Begin End Code Data Used Size Use% Segment Begin End Code Data Used Size Use%
--------------------------------------------------------------- ---------------------------------------------------------------
[.cseg] 0x000000 0x0002d8 676 52 728 2048 35.5% [.cseg] 0x000000 0x000348 788 52 840 2048 41.0%
[.dseg] 0x000060 0x000063 0 3 3 128 2.3% [.dseg] 0x000060 0x000063 0 3 3 128 2.3%
[.eseg] 0x000000 0x000000 0 0 0 128 0.0% [.eseg] 0x000000 0x000000 0 0 0 128 0.0%