From b5abefe7c263121463c4d2fbe4a94520e081a855 Mon Sep 17 00:00:00 2001 From: Sergey Yarkov Date: Wed, 4 May 2022 20:19:16 +0300 Subject: [PATCH] feat: added game level --- firmware.asm | 33 ++- firmware.hex | 101 +++---- firmware.lss | 777 ++++++++++++++++++++++++++------------------------- 3 files changed, 469 insertions(+), 442 deletions(-) diff --git a/firmware.asm b/firmware.asm index 816c64c..6af30c3 100644 --- a/firmware.asm +++ b/firmware.asm @@ -15,6 +15,7 @@ ; ; Registers +.def seq_length_r = r10 ; Current length of sequence .def temp_r = r16 ; Temp general register A .def temp_r_b = r23 ; Temp general register B .def temp_r_c = r26 ; Temp general register C @@ -149,24 +150,28 @@ MCU_Init: ; This function executes once on start the main program rcall init_interrupts rcall init_buzzer + ; + ; Init important registers for game ldi delay_counter_r, 0xff ldi poll_step_r, 1 + ldi temp_r_c, SEQ_LENGTH + mov seq_length_r, temp_r_c clr ZH ldi ZL, $80 - ;rcall MCU_Delay ; Wait 1 sec before start main program + rcall MCU_Delay ; Wait 1 sec before start main program sei ; Enable Global Interrupts ret MCU_Delay: - ldi temp_r, 6 + ldi temp_r_b, 3 _init_loop_loading: rcall effect_1 - dec temp_r + dec temp_r_b brne _init_loop_loading rcall delay_1s - clr temp_r + clr temp_r_b ret ; @@ -251,7 +256,6 @@ btn_handler: ; Check the input value with answer in SRAM rcall delay_50ms rcall delay_50ms rcall delay_50ms - rcall delay_50ms in temp_r_c, PINA mov r25, temp_r_c andi temp_r_c, 0xf0 @@ -263,7 +267,7 @@ btn_handler: ; Check the input value with answer in SRAM cp r25, r24 ; Check answer brne _game_over ; Game over - ldi r18, SEQ_LENGTH + mov r18, seq_length_r cp r18, poll_step_r breq _btn_handler_exit_state @@ -274,6 +278,9 @@ btn_handler: ; Check the input value with answer in SRAM _game_over: rcall effect_1 ldi delay_counter_r, 0xff + ldi temp_r_c, SEQ_LENGTH + dec temp_r_c + mov seq_length_r, temp_r_c _btn_handler_exit_state: pop r18 @@ -285,6 +292,7 @@ btn_handler: ; Check the input value with answer in SRAM rcall delay_1s set_state SHOWING_STATE ldi poll_step_r, 1 + inc seq_length_r ret _btn_handler_exit: pop r18 @@ -292,7 +300,7 @@ btn_handler: ; Check the input value with answer in SRAM ret gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM - ldi temp_r_b, SEQ_LENGTH + mov temp_r_b, seq_length_r clr YH ldi YL, $80 _gen_ran_loop: @@ -333,7 +341,7 @@ ret show_sequence: rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} show_start: - ldi temp_r_b, SEQ_LENGTH + mov temp_r_b, seq_length_r clr YH ldi YL, $80 @@ -370,7 +378,7 @@ show_sequence: beep_4: beep_led_4 rcall OCR0A_reset - beep_quit: + beep_quit: rcall delay dec temp_r_b cpi temp_r_b, 0 @@ -402,6 +410,7 @@ effect_1: ; Shift bits of an leds in port every 50ms push r18 push r19 push r20 + cli in r20, LED_PORT outi LED_PORT, 0xf1 @@ -430,7 +439,7 @@ effect_1: ; Shift bits of an leds in port every 50ms dec r19 brne _eff_1_shift_r - ; + sei ; Out saved PORT values out LED_PORT, r20 pop r20 @@ -516,6 +525,8 @@ ret delay_1s: ; For 1MHz frequency + push r24 + push r25 .equ outer_count = 100 .equ inner_count = 2499 @@ -529,6 +540,8 @@ _loop: dec r18 brne _reset ldi r18, outer_count + pop r25 + pop r24 ret info: .db "Memory led game. Written by Sergey Yarkov 27.09.2021" \ No newline at end of file diff --git a/firmware.hex b/firmware.hex index 64e3c53..787a230 100644 --- a/firmware.hex +++ b/firmware.hex @@ -1,55 +1,56 @@ :020000020000FC -:100000003BC018950EC01895189518951895189519 +:100000003EC018950EC01895189518951895189516 :1000100018951895189515C0189518951895189550 :1000200018951F932F932FB710916000133031F460 -:1000300019B3107F5AD1109362002FBF2F911F91D7 +:1000300019B3107F62D1109362002FBF2F911F91CF :1000400018957F937FB702C008EA52B7052702953B -:10005000500F7FBF7F91189533D122D127D13FEF29 -:1000600041E0FF27E0E87894089506E0F2D00A9591 -:10007000E9F747D1002708950FED0DBF0027109332 -:1000800061000F9301E0009360000F9110916000F8 -:10009000113041F4E1DF109361000F9302E000930F -:1000A00060000F91123041F488D0109361000F93DB -:1000B00003E0009360000F911330C1F520916200BE -:1000C000203E51F40F930EE806BF0F91D89ABA9ACA -:1000D00031D0D898BA98F2CF20916200203D51F4E7 -:1000E0000F9307E406BF0F91D99ABA9A23D0D998F3 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index 9b5012a..3cf9bf2 100644 --- a/firmware.lss +++ b/firmware.lss @@ -1,11 +1,11 @@ -AVRASM ver. 2.2.7 firmware.asm Tue May 03 17:14:17 2022 +AVRASM ver. 2.2.7 firmware.asm Wed May 04 20:17:39 2022 firmware.asm(13): Including file 'def.inc' -firmware.asm(20): warning: Register r26 already defined by the .DEF directive -firmware.asm(73): Including file 'macros.asm' +firmware.asm(21): warning: Register r26 already defined by the .DEF directive +firmware.asm(74): Including file 'macros.asm' firmware.asm(13): Including file 'def.inc' -firmware.asm(73): Including file 'macros.asm' +firmware.asm(74): Including file 'macros.asm' ; Project name: memory-led-game @@ -699,6 +699,7 @@ firmware.asm(73): Including file 'macros.asm' ; ; Registers + .def seq_length_r = r10 ; Current length of sequence .def temp_r = r16 ; Temp general register A .def temp_r_b = r23 ; Temp general register B .def temp_r_c = r26 ; Temp general register C @@ -863,7 +864,7 @@ firmware.asm(73): Including file 'macros.asm' ; ; Setup vectors -000000 c03b rjmp start ; Program start at RESET vector +000000 c03e rjmp start ; Program start at RESET vector 000001 9518 reti ; External Interrupt Request 0 / inactive 000002 c00e rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active 000003 9518 reti ; Pin Change Interrupt Request 1 / inactive @@ -892,7 +893,7 @@ firmware.asm(73): Including file 'macros.asm' 000017 f431 brne quit ; Do not change button flags unless in POLLING state of mcu 000018 b319 in r17, PINA ; Load current pins status of PINA 000019 7f10 andi r17, 0xf0 ; Get pins status of only buttons -00001a d15a rcall delay_50ms ; Delay for button +00001a d162 rcall delay_50ms ; Delay for button 00001b 9310 0062 sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM 00001d bf2f out SREG, r18 @@ -919,485 +920,497 @@ firmware.asm(73): Including file 'macros.asm' 00002b 9518 reti MCU_Init: ; This function executes once on start the main program -00002c d133 rcall init_ports -00002d d122 rcall init_interrupts -00002e d127 rcall init_buzzer +00002c d13b rcall init_ports +00002d d12a rcall init_interrupts +00002e d12f rcall init_buzzer + ; + ; Init important registers for game 00002f ef3f ldi delay_counter_r, 0xff 000030 e041 ldi poll_step_r, 1 -000031 27ff clr ZH -000032 e8e0 ldi ZL, $80 +000031 e0a4 ldi temp_r_c, SEQ_LENGTH +000032 2eaa mov seq_length_r, temp_r_c +000033 27ff clr ZH +000034 e8e0 ldi ZL, $80 - ;rcall MCU_Delay ; Wait 1 sec before start main program +000035 d002 rcall MCU_Delay ; Wait 1 sec before start main program -000033 9478 sei ; Enable Global Interrupts -000034 9508 ret +000036 9478 sei ; Enable Global Interrupts +000037 9508 ret MCU_Delay: -000035 e006 ldi temp_r, 6 +000038 e073 ldi temp_r_b, 3 _init_loop_loading: -000036 d0f2 rcall effect_1 -000037 950a dec temp_r -000038 f7e9 brne _init_loop_loading -000039 d147 rcall delay_1s -00003a 2700 clr temp_r -00003b 9508 ret +000039 d0f5 rcall effect_1 +00003a 957a dec temp_r_b +00003b f7e9 brne _init_loop_loading +00003c d14c rcall delay_1s +00003d 2777 clr temp_r_b +00003e 9508 ret ; ; Program start at reset start: -00003c ed0f -00003d bf0d -00003e 2700 init_stack_p temp_r, RAMEND +00003f ed0f +000040 bf0d +000041 2700 init_stack_p temp_r, RAMEND -00003f 9310 0061 -000041 930f -000042 e001 -000043 9300 0060 -000045 910f set_state INIT_STATE +000042 9310 0061 +000044 930f +000045 e001 +000046 9300 0060 +000048 910f set_state INIT_STATE loop: ; Program loop -000046 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS +000049 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS init: ; Init state -000048 3011 cpi mcu_state_r, INIT_STATE -000049 f441 brne showing -00004a dfe1 rcall MCU_Init -00004b 9310 0061 -00004d 930f -00004e e002 -00004f 9300 0060 -000051 910f set_state SHOWING_STATE +00004b 3011 cpi mcu_state_r, INIT_STATE +00004c f441 brne showing +00004d dfde rcall MCU_Init +00004e 9310 0061 +000050 930f +000051 e002 +000052 9300 0060 +000054 910f set_state SHOWING_STATE showing: ; Showing state -000052 3012 cpi mcu_state_r, SHOWING_STATE -000053 f441 brne polling -000054 d088 rcall show_sequence ; Generate sequence and save answer to SRAM -000055 9310 0061 -000057 930f -000058 e003 -000059 9300 0060 -00005b 910f set_state POLLING_STATE +000055 3012 cpi mcu_state_r, SHOWING_STATE +000056 f441 brne polling +000057 d08b rcall show_sequence ; Generate sequence and save answer to SRAM +000058 9310 0061 +00005a 930f +00005b e003 +00005c 9300 0060 +00005e 910f set_state POLLING_STATE polling: ; Polling state -00005c 3013 cpi mcu_state_r, POLLING_STATE -00005d f5c1 brne completion +00005f 3013 cpi mcu_state_r, POLLING_STATE +000060 f5c1 brne completion btn_1: -00005e 9120 0062 lds r18, SW_FLAGS_ADDRESS -000060 3e20 cpi r18, SW_FLAG_1 -000061 f451 brne btn_2 ; Check next button +000061 9120 0062 lds r18, SW_FLAGS_ADDRESS +000063 3e20 cpi r18, SW_FLAG_1 +000064 f451 brne btn_2 ; Check next button led_on_1: -000062 930f -000063 e80e -000064 bf06 -000065 910f outi OCR0A, 142 -000066 9ad8 sbi LED_PORT, 0 -000067 9aba sbi BUZZ_DIR, BUZZ_PIN -000068 d031 rcall btn_handler -000069 98d8 cbi LED_PORT, 0 -00006a 98ba cbi BUZZ_DIR, BUZZ_PIN -00006b cff2 rjmp btn_1 +000065 930f +000066 e80e +000067 bf06 +000068 910f outi OCR0A, 142 +000069 9ad8 sbi LED_PORT, 0 +00006a 9aba sbi BUZZ_DIR, BUZZ_PIN +00006b d031 rcall btn_handler +00006c 98d8 cbi LED_PORT, 0 +00006d 98ba cbi BUZZ_DIR, BUZZ_PIN +00006e cff2 rjmp btn_1 btn_2: -00006c 9120 0062 lds r18, SW_FLAGS_ADDRESS -00006e 3d20 cpi r18, SW_FLAG_2 -00006f f451 brne btn_3 +00006f 9120 0062 lds r18, SW_FLAGS_ADDRESS +000071 3d20 cpi r18, SW_FLAG_2 +000072 f451 brne btn_3 led_on_2: -000070 930f -000071 e407 -000072 bf06 -000073 910f outi OCR0A, 71 -000074 9ad9 sbi LED_PORT, 1 -000075 9aba sbi BUZZ_DIR, BUZZ_PIN -000076 d023 rcall btn_handler -000077 98d9 cbi LED_PORT, 1 -000078 98ba cbi BUZZ_DIR, BUZZ_PIN -000079 cff2 rjmp btn_2 +000073 930f +000074 e407 +000075 bf06 +000076 910f outi OCR0A, 71 +000077 9ad9 sbi LED_PORT, 1 +000078 9aba sbi BUZZ_DIR, BUZZ_PIN +000079 d023 rcall btn_handler +00007a 98d9 cbi LED_PORT, 1 +00007b 98ba cbi BUZZ_DIR, BUZZ_PIN +00007c cff2 rjmp btn_2 btn_3: -00007a 9120 0062 lds r18, SW_FLAGS_ADDRESS -00007c 3b20 cpi r18, SW_FLAG_3 -00007d f451 brne btn_4 +00007d 9120 0062 lds r18, SW_FLAGS_ADDRESS +00007f 3b20 cpi r18, SW_FLAG_3 +000080 f451 brne btn_4 led_on_3: -00007e 930f -00007f e609 -000080 bf06 -000081 910f outi OCR0A, 105 -000082 9ada sbi LED_PORT, 2 -000083 9aba sbi BUZZ_DIR, BUZZ_PIN -000084 d015 rcall btn_handler -000085 98da cbi LED_PORT, 2 -000086 98ba cbi BUZZ_DIR, BUZZ_PIN -000087 cff2 rjmp btn_3 +000081 930f +000082 e609 +000083 bf06 +000084 910f outi OCR0A, 105 +000085 9ada sbi LED_PORT, 2 +000086 9aba sbi BUZZ_DIR, BUZZ_PIN +000087 d015 rcall btn_handler +000088 98da cbi LED_PORT, 2 +000089 98ba cbi BUZZ_DIR, BUZZ_PIN +00008a cff2 rjmp btn_3 btn_4: -000088 9120 0062 lds r18, SW_FLAGS_ADDRESS -00008a 3720 cpi r18, SW_FLAG_4 -00008b f461 brne default +00008b 9120 0062 lds r18, SW_FLAGS_ADDRESS +00008d 3720 cpi r18, SW_FLAG_4 +00008e f461 brne default led_on_4: -00008c 930f -00008d e500 -00008e bf06 -00008f 910f outi OCR0A, 80 -000090 9adb sbi LED_PORT, 3 -000091 9aba sbi BUZZ_DIR, BUZZ_PIN -000092 d007 rcall btn_handler -000093 98db cbi LED_PORT, 3 -000094 98ba cbi BUZZ_DIR, BUZZ_PIN -000095 cff2 rjmp btn_4 +00008f 930f +000090 e500 +000091 bf06 +000092 910f outi OCR0A, 80 +000093 9adb sbi LED_PORT, 3 +000094 9aba sbi BUZZ_DIR, BUZZ_PIN +000095 d007 rcall btn_handler +000096 98db cbi LED_PORT, 3 +000097 98ba cbi BUZZ_DIR, BUZZ_PIN +000098 cff2 rjmp btn_4 completion: ; Reset delay counter, set MCU state to SHOWING -000096 3014 cpi mcu_state_r, COMPLETION_STATE -000097 f401 brne default +000099 3014 cpi mcu_state_r, COMPLETION_STATE +00009a f401 brne default default: -000098 d085 rcall OCR0A_reset -000099 cfac rjmp loop +00009b d088 rcall OCR0A_reset +00009c cfac rjmp loop btn_handler: ; Check the input value with answer in SRAM -00009a 932f push r18 -00009b d0d9 rcall delay_50ms -00009c d0d8 rcall delay_50ms -00009d d0d7 rcall delay_50ms -00009e d0d6 rcall delay_50ms -00009f b3a9 in temp_r_c, PINA -0000a0 2f9a mov r25, temp_r_c -0000a1 7fa0 andi temp_r_c, 0xf0 -0000a2 709f andi r25, 0x0f -0000a3 27aa clr temp_r_c -0000a4 93a0 0062 sts SW_FLAGS_ADDRESS, temp_r_c +00009d 932f push r18 +00009e d0de rcall delay_50ms +00009f d0dd rcall delay_50ms +0000a0 d0dc rcall delay_50ms +0000a1 b3a9 in temp_r_c, PINA +0000a2 2f9a mov r25, temp_r_c +0000a3 7fa0 andi temp_r_c, 0xf0 +0000a4 709f andi r25, 0x0f +0000a5 27aa clr temp_r_c +0000a6 93a0 0062 sts SW_FLAGS_ADDRESS, temp_r_c -0000a6 9181 ld r24, Z+ -0000a7 1798 cp r25, r24 ; Check answer -0000a8 f429 brne _game_over ; Game over +0000a8 9181 ld r24, Z+ +0000a9 1798 cp r25, r24 ; Check answer +0000aa f429 brne _game_over ; Game over -0000a9 e024 ldi r18, SEQ_LENGTH -0000aa 1724 cp r18, poll_step_r -0000ab f021 breq _btn_handler_exit_state +0000ab 2d2a mov r18, seq_length_r +0000ac 1724 cp r18, poll_step_r +0000ad f039 breq _btn_handler_exit_state -0000ac 9543 inc poll_step_r +0000ae 9543 inc poll_step_r -0000ad c012 rjmp _btn_handler_exit +0000af c016 rjmp _btn_handler_exit _game_over: -0000ae d07a rcall effect_1 -0000af ef3f ldi delay_counter_r, 0xff +0000b0 d07e rcall effect_1 +0000b1 ef3f ldi delay_counter_r, 0xff +0000b2 e0a4 ldi temp_r_c, SEQ_LENGTH +0000b3 95aa dec temp_r_c +0000b4 2eaa mov seq_length_r, temp_r_c _btn_handler_exit_state: -0000b0 912f pop r18 -0000b1 27ff clr ZH -0000b2 e8e0 ldi ZL, $80 -0000b3 98ba cbi BUZZ_DIR, BUZZ_PIN -0000b4 ef00 ldi temp_r, 0xf0 -0000b5 bb0b out LED_PORT, temp_r -0000b6 d0ca rcall delay_1s -0000b7 9310 0061 -0000b9 930f -0000ba e002 -0000bb 9300 0060 -0000bd 910f set_state SHOWING_STATE -0000be e041 ldi poll_step_r, 1 -0000bf 9508 ret +0000b5 912f pop r18 +0000b6 27ff clr ZH +0000b7 e8e0 ldi ZL, $80 +0000b8 98ba cbi BUZZ_DIR, BUZZ_PIN +0000b9 ef00 ldi temp_r, 0xf0 +0000ba bb0b out LED_PORT, temp_r +0000bb d0cd rcall delay_1s +0000bc 9310 0061 +0000be 930f +0000bf e002 +0000c0 9300 0060 +0000c2 910f set_state SHOWING_STATE +0000c3 e041 ldi poll_step_r, 1 +0000c4 94a3 inc seq_length_r +0000c5 9508 ret _btn_handler_exit: -0000c0 912f pop r18 -0000c1 9508 ret -0000c2 9508 ret +0000c6 912f pop r18 +0000c7 9508 ret +0000c8 9508 ret gen_ran_seq: ; Generate random sequence of bytes for leds and save answer to SRAM -0000c3 e074 ldi temp_r_b, SEQ_LENGTH -0000c4 27dd clr YH -0000c5 e8c0 ldi YL, $80 +0000c9 2d7a mov temp_r_b, seq_length_r +0000ca 27dd clr YH +0000cb e8c0 ldi YL, $80 _gen_ran_loop: -0000c6 d0ae rcall delay_50ms ; Delay is required! -0000c7 2f65 mov r22, r21 +0000cc d0b0 rcall delay_50ms ; Delay is required! +0000cd 2f65 mov r22, r21 -0000c8 3466 cpi r22, 70 -0000c9 f030 brlo _gen_answ_1 +0000ce 3466 cpi r22, 70 +0000cf f030 brlo _gen_answ_1 -0000ca 386c cpi r22, 140 -0000cb f030 brlo _gen_answ_2 +0000d0 386c cpi r22, 140 +0000d1 f030 brlo _gen_answ_2 -0000cc 3c68 cpi r22, 200 -0000cd f030 brlo _gen_answ_3 +0000d2 3c68 cpi r22, 200 +0000d3 f030 brlo _gen_answ_3 -0000ce 3f6f cpi r22, 255 -0000cf f030 brlo _gen_answ_4 +0000d4 3f6f cpi r22, 255 +0000d5 f030 brlo _gen_answ_4 _gen_answ_1: -0000d0 e0a1 ldi temp_r_c, 0x01 -0000d1 c005 rjmp _gen_ran_write +0000d6 e0a1 ldi temp_r_c, 0x01 +0000d7 c005 rjmp _gen_ran_write _gen_answ_2: -0000d2 e0a2 ldi temp_r_c, 0x02 -0000d3 c003 rjmp _gen_ran_write +0000d8 e0a2 ldi temp_r_c, 0x02 +0000d9 c003 rjmp _gen_ran_write _gen_answ_3: -0000d4 e0a4 ldi temp_r_c, 0x04 -0000d5 c001 rjmp _gen_ran_write +0000da e0a4 ldi temp_r_c, 0x04 +0000db c001 rjmp _gen_ran_write _gen_answ_4: -0000d6 e0a8 ldi temp_r_c, 0x08 +0000dc e0a8 ldi temp_r_c, 0x08 _gen_ran_write: -0000d7 93a9 st Y+, temp_r_c -0000d8 957a dec temp_r_b -0000d9 3070 cpi temp_r_b, 0 -0000da f759 brne _gen_ran_loop -0000db 0000 nop -0000dc 9508 ret +0000dd 93a9 st Y+, temp_r_c +0000de 957a dec temp_r_b +0000df 3070 cpi temp_r_b, 0 +0000e0 f759 brne _gen_ran_loop +0000e1 0000 nop +0000e2 9508 ret show_sequence: -0000dd dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} +0000e3 dfe5 rcall gen_ran_seq ; Answer stored in SRAM in addr $80:{SEQ_LENGTH} show_start: -0000de e074 ldi temp_r_b, SEQ_LENGTH +0000e4 2d7a mov temp_r_b, seq_length_r -0000df 27dd clr YH -0000e0 e8c0 ldi YL, $80 +0000e5 27dd clr YH +0000e6 e8c0 ldi YL, $80 _sequence_loop: -0000e1 3070 cpi temp_r_b, 0 -0000e2 f1c1 breq _seq_quit +0000e7 3070 cpi temp_r_b, 0 +0000e8 f1c1 breq _seq_quit -0000e3 91a9 ld temp_r_c, Y+ -0000e4 30a1 cpi temp_r_c, 0x01 -0000e5 f031 breq beep_1 +0000e9 91a9 ld temp_r_c, Y+ +0000ea 30a1 cpi temp_r_c, 0x01 +0000eb f031 breq beep_1 -0000e6 30a2 cpi temp_r_c, 0x02 -0000e7 f079 breq beep_2 +0000ec 30a2 cpi temp_r_c, 0x02 +0000ed f079 breq beep_2 -0000e8 30a4 cpi temp_r_c, 0x04 -0000e9 f0c1 breq beep_3 +0000ee 30a4 cpi temp_r_c, 0x04 +0000ef f0c1 breq beep_3 -0000ea 30a8 cpi temp_r_c, 0x08 -0000eb f109 breq beep_4 +0000f0 30a8 cpi temp_r_c, 0x08 +0000f1 f109 breq beep_4 beep_1: -0000ec 930f -0000ed e80e -0000ee bf06 -0000ef 910f -0000f0 9ad8 -0000f1 9aba -0000f2 d074 -0000f3 98d8 -0000f4 98ba beep_led_1 -0000f5 d028 rcall OCR0A_reset -0000f6 c020 rjmp beep_quit +0000f2 930f +0000f3 e80e +0000f4 bf06 +0000f5 910f +0000f6 9ad8 +0000f7 9aba +0000f8 d076 +0000f9 98d8 +0000fa 98ba beep_led_1 +0000fb d028 rcall OCR0A_reset +0000fc c020 rjmp beep_quit beep_2: -0000f7 930f -0000f8 e407 -0000f9 bf06 -0000fa 910f -0000fb 9ad9 -0000fc 9aba -0000fd d069 -0000fe 98d9 -0000ff 98ba beep_led_2 -000100 d01d rcall OCR0A_reset -000101 c015 rjmp beep_quit +0000fd 930f +0000fe e407 +0000ff bf06 +000100 910f +000101 9ad9 +000102 9aba +000103 d06b +000104 98d9 +000105 98ba beep_led_2 +000106 d01d rcall OCR0A_reset +000107 c015 rjmp beep_quit beep_3: -000102 930f -000103 e609 -000104 bf06 -000105 910f -000106 9ada -000107 9aba -000108 d05e -000109 98da -00010a 98ba beep_led_3 -00010b d012 rcall OCR0A_reset -00010c c00a rjmp beep_quit +000108 930f +000109 e609 +00010a bf06 +00010b 910f +00010c 9ada +00010d 9aba +00010e d060 +00010f 98da +000110 98ba beep_led_3 +000111 d012 rcall OCR0A_reset +000112 c00a rjmp beep_quit beep_4: -00010d 930f -00010e e500 -00010f bf06 -000110 910f -000111 9adb -000112 9aba -000113 d053 -000114 98db -000115 98ba beep_led_4 -000116 d007 rcall OCR0A_reset - beep_quit: -000117 d04f rcall delay -000118 957a dec temp_r_b -000119 3070 cpi temp_r_b, 0 -00011a f631 brne _sequence_loop +000113 930f +000114 e500 +000115 bf06 +000116 910f +000117 9adb +000118 9aba +000119 d055 +00011a 98db +00011b 98ba beep_led_4 +00011c d007 rcall OCR0A_reset + beep_quit: +00011d d051 rcall delay +00011e 957a dec temp_r_b +00011f 3070 cpi temp_r_b, 0 +000120 f631 brne _sequence_loop _seq_quit: -00011b d007 rcall dec_delay_counter -00011c d058 rcall delay_50ms -00011d 9508 ret +000121 d007 rcall dec_delay_counter +000122 d05a rcall delay_50ms +000123 9508 ret OCR0A_reset: ; This function need to set the OCR0A register to 0xff for overflow interrupt -00011e 937f push temp_r_b -00011f ef7f ldi temp_r_b, 0xff -000120 bf76 out OCR0A, temp_r_b -000121 917f pop temp_r_b -000122 9508 ret - - dec_delay_counter: -000123 503a subi delay_counter_r, 10 -000124 3238 cpi delay_counter_r, 40 -000125 f008 brlo _reset_counter -000126 9508 ret - _reset_counter: -000127 ef3f ldi delay_counter_r, 0xff +000124 937f push temp_r_b +000125 ef7f ldi temp_r_b, 0xff +000126 bf76 out OCR0A, temp_r_b +000127 917f pop temp_r_b 000128 9508 ret + dec_delay_counter: +000129 503a subi delay_counter_r, 10 +00012a 3238 cpi delay_counter_r, 40 +00012b f008 brlo _reset_counter +00012c 9508 ret + _reset_counter: +00012d ef3f ldi delay_counter_r, 0xff +00012e 9508 ret + effect_1: ; Shift bits of an leds in port every 50ms -000129 931f push r17 -00012a 932f push r18 -00012b 933f push r19 -00012c 934f push r20 -00012d b34b in r20, LED_PORT +00012f 931f push r17 +000130 932f push r18 +000131 933f push r19 +000132 934f push r20 +000133 94f8 cli +000134 b34b in r20, LED_PORT -00012e 930f -00012f ef01 -000130 bb0b -000131 910f outi LED_PORT, 0xf1 -000132 d042 rcall delay_50ms -000133 e011 ldi r17, 0x01 -000134 e033 ldi r19, 3 +000135 930f +000136 ef01 +000137 bb0b +000138 910f outi LED_PORT, 0xf1 +000139 d043 rcall delay_50ms +00013a e011 ldi r17, 0x01 +00013b e033 ldi r19, 3 _eff_1_shift_l: ; Shift bits to left loop -000135 ef20 ldi r18, 0xf0 -000136 0f11 lsl r17 -000137 0f21 add r18, r17 -000138 bb2b out LED_PORT, r18 -000139 d03b rcall delay_50ms -00013a 953a dec r19 -00013b f7c9 brne _eff_1_shift_l +00013c ef20 ldi r18, 0xf0 +00013d 0f11 lsl r17 +00013e 0f21 add r18, r17 +00013f bb2b out LED_PORT, r18 +000140 d03c rcall delay_50ms +000141 953a dec r19 +000142 f7c9 brne _eff_1_shift_l -00013c 930f -00013d ef08 -00013e bb0b -00013f 910f outi LED_PORT, 0xf8 -000140 d034 rcall delay_50ms -000141 e018 ldi r17, 0x08 -000142 e033 ldi r19, 3 +000143 930f +000144 ef08 +000145 bb0b +000146 910f outi LED_PORT, 0xf8 +000147 d035 rcall delay_50ms +000148 e018 ldi r17, 0x08 +000149 e033 ldi r19, 3 _eff_1_shift_r: ; Shift bits to right loop -000143 ef20 ldi r18, 0xf0 -000144 9516 lsr r17 -000145 0f21 add r18, r17 -000146 bb2b out LED_PORT, r18 -000147 d02d rcall delay_50ms -000148 953a dec r19 -000149 f7c9 brne _eff_1_shift_r +00014a ef20 ldi r18, 0xf0 +00014b 9516 lsr r17 +00014c 0f21 add r18, r17 +00014d bb2b out LED_PORT, r18 +00014e d02e rcall delay_50ms +00014f 953a dec r19 +000150 f7c9 brne _eff_1_shift_r - ; +000151 9478 sei ; Out saved PORT values -00014a bb4b out LED_PORT, r20 -00014b 914f pop r20 -00014c 913f pop r19 -00014d 912f pop r18 -00014e 911f pop r17 -00014f 9508 ret +000152 bb4b out LED_PORT, r20 +000153 914f pop r20 +000154 913f pop r19 +000155 912f pop r18 +000156 911f pop r17 +000157 9508 ret init_interrupts: ; ; Enable Port Change Interrupt -000150 e100 ldi temp_r, (1<