AVRASM ver. 2.2.7  firmware.asm Sun May 22 21:06:03 2022

firmware.asm(13): Including file 'def.inc'
firmware.asm(21): warning: Register r26 already defined by the .DEF directive
firmware.asm(73): Including file 'macros.asm'
firmware.asm(13): Including file 'def.inc'
firmware.asm(73): Including file 'macros.asm'
                                 
                                 
                                 ; Project name: memory-led-game
                                 ; Description: Simple memory game using leds
                                 ; Source code: https://github.com/sergeyyarkov/attiny24a_memory-led-game
                                 ; Device: ATtiny24A
                                 ; Package: 14-pin-PDIP_SOIC
                                 ; Assembler: AVR macro assembler 2.2.7
                                 ; Clock frequency: 8MHz with CKDIV8
                                 ; Fuses: lfuse: 0x42, hfuse: 0xDF, efuse: 0xFF, lock:0xFF
                                 ;
                                 ; Written by Sergey Yarkov 27.09.2021
                                 
                                 .include "def.inc"					; Include type definitions of MCU
                                 
                                 ;***** Created: 2011-02-09 12:04 ******* Source: ATtiny24A.xml ***********
                                 ;*************************************************************************
                                 ;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
                                 ;* 
                                 ;* Number            : AVR000
                                 ;* File Name         : "tn24Adef.inc"
                                 ;* Title             : Register/Bit Definitions for the ATtiny24A
                                 ;* Date              : 2011-02-09
                                 ;* Version           : 2.35
                                 ;* Support E-mail    : avr@atmel.com
                                 ;* Target MCU        : ATtiny24A
                                 ;* 
                                 ;* DESCRIPTION
                                 ;* When including this file in the assembly program file, all I/O register 
                                 ;* names and I/O register bit names appearing in the data book can be used.
                                 ;* In addition, the six registers forming the three data pointers X, Y and 
                                 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
                                 ;* SRAM is also defined 
                                 ;* 
                                 ;* The Register names are represented by their hexadecimal address.
                                 ;* 
                                 ;* The Register Bit names are represented by their bit number (0-7).
                                 ;* 
                                 ;* Please observe the difference in using the bit names with instructions
                                 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
                                 ;* (skip if bit in register set/cleared). The following example illustrates
                                 ;* this:
                                 ;* 
                                 ;* in    r16,PORTB             ;read PORTB latch
                                 ;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
                                 ;* out   PORTB,r16             ;output to PORTB
                                 ;* 
                                 ;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
                                 ;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
                                 ;* rjmp  TOV0_is_set           ;jump if set
                                 ;* ...                         ;otherwise do something else
                                 ;*************************************************************************
                                 
                                 #ifndef _TN24ADEF_INC_
                                 #define _TN24ADEF_INC_
                                 
                                 
                                 #pragma partinc 0
                                 
                                 ; ***** SPECIFY DEVICE ***************************************************
                                 .device ATtiny24A
                                 #pragma AVRPART ADMIN PART_NAME ATtiny24A
                                 .equ	SIGNATURE_000	= 0x1e
                                 .equ	SIGNATURE_001	= 0x91
                                 .equ	SIGNATURE_002	= 0x0b
                                 
                                 #pragma AVRPART CORE CORE_VERSION V2
                                 #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
                                 
                                 
                                 ; ***** I/O REGISTER DEFINITIONS *****************************************
                                 ; NOTE:
                                 ; Definitions marked "MEMORY MAPPED"are extended I/O ports
                                 ; and cannot be used with IN/OUT instructions
                                 .equ	SREG	= 0x3f
                                 .equ	SPL	= 0x3d
                                 .equ	OCR0B	= 0x3c
                                 .equ	GIMSK	= 0x3b
                                 .equ	GIFR	= 0x3a
                                 .equ	TIMSK0	= 0x39
                                 .equ	TIFR0	= 0x38
                                 .equ	SPMCSR	= 0x37
                                 .equ	OCR0A	= 0x36
                                 .equ	MCUCR	= 0x35
                                 .equ	MCUSR	= 0x34
                                 .equ	TCCR0B	= 0x33
                                 .equ	TCNT0	= 0x32
                                 .equ	OSCCAL	= 0x31
                                 .equ	TCCR0A	= 0x30
                                 .equ	TCCR1A	= 0x2f
                                 .equ	TCCR1B	= 0x2e
                                 .equ	TCNT1L	= 0x2c
                                 .equ	TCNT1H	= 0x2d
                                 .equ	OCR1AL	= 0x2a
                                 .equ	OCR1AH	= 0x2b
                                 .equ	OCR1BL	= 0x28
                                 .equ	OCR1BH	= 0x29
                                 .equ	DWDR	= 0x27
                                 .equ	CLKPR	= 0x26
                                 .equ	ICR1L	= 0x24
                                 .equ	ICR1H	= 0x25
                                 .equ	GTCCR	= 0x23
                                 .equ	TCCR1C	= 0x22
                                 .equ	WDTCSR	= 0x21
                                 .equ	PCMSK1	= 0x20
                                 .equ	EEARH	= 0x1f
                                 .equ	EEARL	= 0x1e
                                 .equ	EEDR	= 0x1d
                                 .equ	EECR	= 0x1c
                                 .equ	PORTA	= 0x1b
                                 .equ	DDRA	= 0x1a
                                 .equ	PINA	= 0x19
                                 .equ	PORTB	= 0x18
                                 .equ	DDRB	= 0x17
                                 .equ	PINB	= 0x16
                                 .equ	GPIOR2	= 0x15
                                 .equ	GPIOR1	= 0x14
                                 .equ	GPIOR0	= 0x13
                                 .equ	PCMSK0	= 0x12
                                 .equ	USIBR	= 0x10
                                 .equ	USIDR	= 0x0f
                                 .equ	USISR	= 0x0e
                                 .equ	USICR	= 0x0d
                                 .equ	TIMSK1	= 0x0c
                                 .equ	TIFR1	= 0x0b
                                 .equ	ACSR	= 0x08
                                 .equ	ADMUX	= 0x07
                                 .equ	ADCSRA	= 0x06
                                 .equ	ADCH	= 0x05
                                 .equ	ADCL	= 0x04
                                 .equ	ADCSRB	= 0x03
                                 .equ	DIDR0	= 0x01
                                 .equ	PRR	= 0x00
                                 
                                 
                                 ; ***** BIT DEFINITIONS **************************************************
                                 
                                 ; ***** PORTA ************************
                                 ; PORTA - Port A Data Register
                                 .equ	PORTA0	= 0	; Port A Data Register bit 0
                                 .equ	PA0	= 0	; For compatibility
                                 .equ	PORTA1	= 1	; Port A Data Register bit 1
                                 .equ	PA1	= 1	; For compatibility
                                 .equ	PORTA2	= 2	; Port A Data Register bit 2
                                 .equ	PA2	= 2	; For compatibility
                                 .equ	PORTA3	= 3	; Port A Data Register bit 3
                                 .equ	PA3	= 3	; For compatibility
                                 .equ	PORTA4	= 4	; Port A Data Register bit 4
                                 .equ	PA4	= 4	; For compatibility
                                 .equ	PORTA5	= 5	; Port A Data Register bit 5
                                 .equ	PA5	= 5	; For compatibility
                                 .equ	PORTA6	= 6	; Port A Data Register bit 6
                                 .equ	PA6	= 6	; For compatibility
                                 .equ	PORTA7	= 7	; Port A Data Register bit 7
                                 .equ	PA7	= 7	; For compatibility
                                 
                                 ; DDRA - Port A Data Direction Register
                                 .equ	DDA0	= 0	; Data Direction Register, Port A, bit 0
                                 .equ	DDA1	= 1	; Data Direction Register, Port A, bit 1
                                 .equ	DDA2	= 2	; Data Direction Register, Port A, bit 2
                                 .equ	DDA3	= 3	; Data Direction Register, Port A, bit 3
                                 .equ	DDA4	= 4	; Data Direction Register, Port A, bit 4
                                 .equ	DDA5	= 5	; Data Direction Register, Port A, bit 5
                                 .equ	DDA6	= 6	; Data Direction Register, Port A, bit 6
                                 .equ	DDA7	= 7	; Data Direction Register, Port A, bit 7
                                 
                                 ; PINA - Port A Input Pins
                                 .equ	PINA0	= 0	; Input Pins, Port A bit 0
                                 .equ	PINA1	= 1	; Input Pins, Port A bit 1
                                 .equ	PINA2	= 2	; Input Pins, Port A bit 2
                                 .equ	PINA3	= 3	; Input Pins, Port A bit 3
                                 .equ	PINA4	= 4	; Input Pins, Port A bit 4
                                 .equ	PINA5	= 5	; Input Pins, Port A bit 5
                                 .equ	PINA6	= 6	; Input Pins, Port A bit 6
                                 .equ	PINA7	= 7	; Input Pins, Port A bit 7
                                 
                                 
                                 ; ***** PORTB ************************
                                 ; PORTB - Data Register, Port B
                                 .equ	PORTB0	= 0	; 
                                 .equ	PB0	= 0	; For compatibility
                                 .equ	PORTB1	= 1	; 
                                 .equ	PB1	= 1	; For compatibility
                                 .equ	PORTB2	= 2	; 
                                 .equ	PB2	= 2	; For compatibility
                                 .equ	PORTB3	= 3	; 
                                 .equ	PB3	= 3	; For compatibility
                                 
                                 ; DDRB - Data Direction Register, Port B
                                 .equ	DDB0	= 0	; 
                                 .equ	DDB1	= 1	; 
                                 .equ	DDB2	= 2	; 
                                 .equ	DDB3	= 3	; 
                                 
                                 ; PINB - Input Pins, Port B
                                 .equ	PINB0	= 0	; 
                                 .equ	PINB1	= 1	; 
                                 .equ	PINB2	= 2	; 
                                 .equ	PINB3	= 3	; 
                                 
                                 
                                 ; ***** ANALOG_COMPARATOR ************
                                 ; ADCSRB - ADC Control and Status Register B
                                 .equ	ACME	= 6	; Analog Comparator Multiplexer Enable
                                 
                                 ; ACSR - Analog Comparator Control And Status Register
                                 .equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
                                 .equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
                                 .equ	ACIC	= 2	; Analog Comparator Input Capture Enable
                                 .equ	ACIE	= 3	; Analog Comparator Interrupt Enable
                                 .equ	ACI	= 4	; Analog Comparator Interrupt Flag
                                 .equ	ACO	= 5	; Analog Compare Output
                                 .equ	ACBG	= 6	; Analog Comparator Bandgap Select
                                 .equ	AINBG	= ACBG	; For compatibility
                                 .equ	ACD	= 7	; Analog Comparator Disable
                                 
                                 ; DIDR0 - 
                                 .equ	ADC0D	= 0	; ADC 0 Digital input buffer disable
                                 .equ	ADC1D	= 1	; ADC 1 Digital input buffer disable
                                 
                                 
                                 ; ***** AD_CONVERTER *****************
                                 ; ADMUX - ADC Multiplexer Selection Register
                                 .equ	MUX0	= 0	; Analog Channel and Gain Selection Bit 0
                                 .equ	MUX1	= 1	; Analog Channel and Gain Selection Bit 1
                                 .equ	MUX2	= 2	; Analog Channel and Gain Selection Bit 2
                                 .equ	MUX3	= 3	; Analog Channel and Gain Selection Bit 3
                                 .equ	MUX4	= 4	; Analog Channel and Gain Selection Bit 4
                                 .equ	MUX5	= 5	; Analog Channel and Gain Selection Bit 5
                                 .equ	REFS0	= 6	; Reference Selection Bit 0
                                 .equ	REFS1	= 7	; Reference Selection Bit 1
                                 
                                 ; ADCSRA - ADC Control and Status Register A
                                 .equ	ADPS0	= 0	; ADC  Prescaler Select Bit 0
                                 .equ	ADPS1	= 1	; ADC  Prescaler Select Bit 1
                                 .equ	ADPS2	= 2	; ADC  Prescaler Select Bit 2
                                 .equ	ADIE	= 3	; ADC Interrupt Enable
                                 .equ	ADIF	= 4	; ADC Interrupt Flag
                                 .equ	ADATE	= 5	; ADC Auto Trigger Enable
                                 .equ	ADSC	= 6	; ADC Start Conversion
                                 .equ	ADEN	= 7	; ADC Enable
                                 
                                 ; ADCH - ADC Data Register High Byte
                                 .equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
                                 .equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
                                 .equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
                                 .equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
                                 .equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
                                 .equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
                                 .equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
                                 .equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7
                                 
                                 ; ADCL - ADC Data Register Low Byte
                                 .equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
                                 .equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
                                 .equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
                                 .equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
                                 .equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
                                 .equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
                                 .equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
                                 .equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7
                                 
                                 ; ADCSRB - ADC Control and Status Register B
                                 .equ	ADTS0	= 0	; ADC Auto Trigger Source bit 0
                                 .equ	ADTS1	= 1	; ADC Auto Trigger Source bit 1
                                 .equ	ADTS2	= 2	; ADC Auto Trigger Source bit 2
                                 .equ	ADLAR	= 4	; ADC Left Adjust Result
                                 .equ	BIN	= 7	; Bipolar Input Mode
                                 
                                 ; DIDR0 - Digital Input Disable Register 0
                                 ;.equ	ADC0D	= 0	; ADC0 Digital Input Disable
                                 ;.equ	ADC1D	= 1	; ADC1 Digital Input Disable
                                 .equ	ADC2D	= 2	; ADC2 Digital Input Disable
                                 .equ	ADC3D	= 3	; ADC3 Digital Input Disable
                                 .equ	ADC4D	= 4	; ADC4 Digital Input Disable
                                 .equ	ADC5D	= 5	; ADC5 Digital Input Disable
                                 .equ	ADC6D	= 6	; ADC6 Digital Input Disable
                                 .equ	ADC7D	= 7	; ADC7 Digital Input Disable
                                 
                                 
                                 ; ***** USI **************************
                                 ; USIBR - USI Buffer Register
                                 .equ	USIBR0	= 0	; USI Buffer Register bit 0
                                 .equ	USIBR1	= 1	; USI Buffer Register bit 1
                                 .equ	USIBR2	= 2	; USI Buffer Register bit 2
                                 .equ	USIBR3	= 3	; USI Buffer Register bit 3
                                 .equ	USIBR4	= 4	; USI Buffer Register bit 4
                                 .equ	USIBR5	= 5	; USI Buffer Register bit 5
                                 .equ	USIBR6	= 6	; USI Buffer Register bit 6
                                 .equ	USIBR7	= 7	; USI Buffer Register bit 7
                                 
                                 ; USIDR - USI Data Register
                                 .equ	USIDR0	= 0	; USI Data Register bit 0
                                 .equ	USIDR1	= 1	; USI Data Register bit 1
                                 .equ	USIDR2	= 2	; USI Data Register bit 2
                                 .equ	USIDR3	= 3	; USI Data Register bit 3
                                 .equ	USIDR4	= 4	; USI Data Register bit 4
                                 .equ	USIDR5	= 5	; USI Data Register bit 5
                                 .equ	USIDR6	= 6	; USI Data Register bit 6
                                 .equ	USIDR7	= 7	; USI Data Register bit 7
                                 
                                 ; USISR - USI Status Register
                                 .equ	USICNT0	= 0	; USI Counter Value Bit 0
                                 .equ	USICNT1	= 1	; USI Counter Value Bit 1
                                 .equ	USICNT2	= 2	; USI Counter Value Bit 2
                                 .equ	USICNT3	= 3	; USI Counter Value Bit 3
                                 .equ	USIDC	= 4	; Data Output Collision
                                 .equ	USIPF	= 5	; Stop Condition Flag
                                 .equ	USIOIF	= 6	; Counter Overflow Interrupt Flag
                                 .equ	USISIF	= 7	; Start Condition Interrupt Flag
                                 
                                 ; USICR - USI Control Register
                                 .equ	USITC	= 0	; Toggle Clock Port Pin
                                 .equ	USICLK	= 1	; Clock Strobe
                                 .equ	USICS0	= 2	; USI Clock Source Select Bit 0
                                 .equ	USICS1	= 3	; USI Clock Source Select Bit 1
                                 .equ	USIWM0	= 4	; USI Wire Mode Bit 0
                                 .equ	USIWM1	= 5	; USI Wire Mode Bit 1
                                 .equ	USIOIE	= 6	; Counter Overflow Interrupt Enable
                                 .equ	USISIE	= 7	; Start Condition Interrupt Enable
                                 
                                 
                                 ; ***** EXTERNAL_INTERRUPT ***********
                                 ; MCUCR - MCU Control Register
                                 .equ	ISC00	= 0	; Interrupt Sense Control 0 Bit 0
                                 .equ	ISC01	= 1	; Interrupt Sense Control 0 Bit 1
                                 
                                 ; GIMSK - General Interrupt Mask Register
                                 .equ	GICR	= GIMSK	; For compatibility
                                 .equ	PCIE0	= 4	; Pin Change Interrupt Enable 0
                                 .equ	PCIE1	= 5	; Pin Change Interrupt Enable 1
                                 .equ	INT0	= 6	; External Interrupt Request 0 Enable
                                 
                                 ; GIFR - General Interrupt Flag register
                                 .equ	PCIF0	= 4	; Pin Change Interrupt Flag 0
                                 .equ	PCIF1	= 5	; Pin Change Interrupt Flag 1
                                 .equ	INTF0	= 6	; External Interrupt Flag 0
                                 
                                 ; PCMSK1 - Pin Change Enable Mask 1
                                 .equ	PCINT8	= 0	; Pin Change Enable Mask Bit 8
                                 .equ	PCINT9	= 1	; Pin Change Enable Mask Bit 9
                                 .equ	PCINT10	= 2	; Pin Change Enable Mask Bit 10
                                 .equ	PCINT11	= 3	; Pin Change Enable Mask Bit 11
                                 
                                 ; PCMSK0 - Pin Change Enable Mask 0
                                 .equ	PCINT0	= 0	; Pin Change Enable Mask Bit 0
                                 .equ	PCINT1	= 1	; Pin Change Enable Mask Bit 1
                                 .equ	PCINT2	= 2	; Pin Change Enable Mask Bit 2
                                 .equ	PCINT3	= 3	; Pin Change Enable Mask Bit 3
                                 .equ	PCINT4	= 4	; Pin Change Enable Mask Bit 4
                                 .equ	PCINT5	= 5	; Pin Change Enable Mask Bit 5
                                 .equ	PCINT6	= 6	; Pin Change Enable Mask Bit 6
                                 .equ	PCINT7	= 7	; Pin Change Enable Mask Bit 7
                                 
                                 
                                 ; ***** EEPROM ***********************
                                 ; EEARL - EEPROM Address Register Low Byte
                                 .equ	EEAR0	= 0	; EEPROM Read/Write Access Bit 0
                                 .equ	EEAR1	= 1	; EEPROM Read/Write Access Bit 1
                                 .equ	EEAR2	= 2	; EEPROM Read/Write Access Bit 2
                                 .equ	EEAR3	= 3	; EEPROM Read/Write Access Bit 3
                                 .equ	EEAR4	= 4	; EEPROM Read/Write Access Bit 4
                                 .equ	EEAR5	= 5	; EEPROM Read/Write Access Bit 5
                                 .equ	EEAR6	= 6	; EEPROM Read/Write Access Bit 6
                                 .equ	EEAR7	= 7	; EEPROM Read/Write Access Bit 7
                                 
                                 ; EEARH - EEPROM Address Register High Byte
                                 .equ	EEAR8	= 0	; EEPROM Read/Write Access Bit 0
                                 
                                 ; EEDR - EEPROM Data Register
                                 .equ	EEDR0	= 0	; EEPROM Data Register bit 0
                                 .equ	EEDR1	= 1	; EEPROM Data Register bit 1
                                 .equ	EEDR2	= 2	; EEPROM Data Register bit 2
                                 .equ	EEDR3	= 3	; EEPROM Data Register bit 3
                                 .equ	EEDR4	= 4	; EEPROM Data Register bit 4
                                 .equ	EEDR5	= 5	; EEPROM Data Register bit 5
                                 .equ	EEDR6	= 6	; EEPROM Data Register bit 6
                                 .equ	EEDR7	= 7	; EEPROM Data Register bit 7
                                 
                                 ; EECR - EEPROM Control Register
                                 .equ	EERE	= 0	; EEPROM Read Enable
                                 .equ	EEPE	= 1	; EEPROM Write Enable
                                 .equ	EEMPE	= 2	; EEPROM Master Write Enable
                                 .equ	EERIE	= 3	; EEPROM Ready Interrupt Enable
                                 .equ	EEPM0	= 4	; EEPROM Programming Mode Bit 0
                                 .equ	EEPM1	= 5	; EEPROM Programming Mode Bit 1
                                 
                                 
                                 ; ***** WATCHDOG *********************
                                 ; WDTCSR - Watchdog Timer Control Register
                                 .equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
                                 .equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
                                 .equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
                                 .equ	WDE	= 3	; Watch Dog Enable
                                 .equ	WDCE	= 4	; Watchdog Change Enable
                                 .equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
                                 .equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
                                 .equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag
                                 
                                 
                                 ; ***** TIMER_COUNTER_0 **************
                                 ; TIMSK0 - Timer/Counter Interrupt Mask Register
                                 .equ	TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
                                 .equ	OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
                                 .equ	OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable
                                 
                                 ; TIFR0 - Timer/Counter0 Interrupt Flag Register
                                 .equ	TOV0	= 0	; Timer/Counter0 Overflow Flag
                                 .equ	OCF0A	= 1	; Timer/Counter0 Output Compare Flag A
                                 .equ	OCF0B	= 2	; Timer/Counter0 Output Compare Flag B
                                 
                                 ; TCCR0A - Timer/Counter  Control Register A
                                 .equ	WGM00	= 0	; Waveform Generation Mode bit 0
                                 .equ	WGM01	= 1	; Waveform Generation Mode bit 1
                                 .equ	COM0B0	= 4	; Compare Match Output B Mode bit 0
                                 .equ	COM0B1	= 5	; Compare Match Output B Mode bit 1
                                 .equ	COM0A0	= 6	; Compare Match Output A Mode bit 0
                                 .equ	COM0A1	= 7	; Compare Match Output A Mode bit 1
                                 
                                 ; TCCR0B - Timer/Counter Control Register B
                                 .equ	CS00	= 0	; Clock Select bit 0
                                 .equ	CS01	= 1	; Clock Select bit 1
                                 .equ	CS02	= 2	; Clock Select bit 2
                                 .equ	WGM02	= 3	; Waveform Generation Mode bit 2
                                 .equ	FOC0B	= 6	; Force Output Compare B
                                 .equ	FOC0A	= 7	; Force Output Compare A
                                 
                                 ; TCNT0 - Timer/Counter0
                                 .equ	TCNT0_0	= 0	; 
                                 .equ	TCNT0_1	= 1	; 
                                 .equ	TCNT0_2	= 2	; 
                                 .equ	TCNT0_3	= 3	; 
                                 .equ	TCNT0_4	= 4	; 
                                 .equ	TCNT0_5	= 5	; 
                                 .equ	TCNT0_6	= 6	; 
                                 .equ	TCNT0_7	= 7	; 
                                 
                                 ; OCR0A - Timer/Counter0 Output Compare Register A
                                 .equ	OCR0A_0	= 0	; 
                                 .equ	OCR0A_1	= 1	; 
                                 .equ	OCR0A_2	= 2	; 
                                 .equ	OCR0A_3	= 3	; 
                                 .equ	OCR0A_4	= 4	; 
                                 .equ	OCR0A_5	= 5	; 
                                 .equ	OCR0A_6	= 6	; 
                                 .equ	OCR0A_7	= 7	; 
                                 
                                 ; OCR0B - Timer/Counter0 Output Compare Register B
                                 .equ	OCR0_0	= 0	; 
                                 .equ	OCR0_1	= 1	; 
                                 .equ	OCR0_2	= 2	; 
                                 .equ	OCR0_3	= 3	; 
                                 .equ	OCR0_4	= 4	; 
                                 .equ	OCR0_5	= 5	; 
                                 .equ	OCR0_6	= 6	; 
                                 .equ	OCR0_7	= 7	; 
                                 
                                 ; GTCCR - General Timer/Counter Control Register
                                 .equ	PSR10	= 0	; Prescaler Reset Timer/CounterN
                                 .equ	TSM	= 7	; Timer/Counter Synchronization Mode
                                 
                                 
                                 ; ***** TIMER_COUNTER_1 **************
                                 ; TIMSK1 - Timer/Counter1 Interrupt Mask Register
                                 .equ	TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
                                 .equ	OCIE1A	= 1	; Timer/Counter1 Output Compare A Match Interrupt Enable
                                 .equ	OCIE1B	= 2	; Timer/Counter1 Output Compare B Match Interrupt Enable
                                 .equ	ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable
                                 
                                 ; TIFR1 - Timer/Counter Interrupt Flag register
                                 .equ	TOV1	= 0	; Timer/Counter1 Overflow Flag
                                 .equ	OCF1A	= 1	; Timer/Counter1 Output Compare A Match Flag
                                 .equ	OCF1B	= 2	; Timer/Counter1 Output Compare B Match Flag
                                 .equ	ICF1	= 5	; Timer/Counter1 Input Capture Flag
                                 
                                 ; TCCR1A - Timer/Counter1 Control Register A
                                 .equ	WGM10	= 0	; Pulse Width Modulator Select Bit 0
                                 .equ	PWM10	= WGM10	; For compatibility
                                 .equ	WGM11	= 1	; Pulse Width Modulator Select Bit 1
                                 .equ	PWM11	= WGM11	; For compatibility
                                 .equ	COM1B0	= 4	; Comparet Ouput Mode 1B, bit 0
                                 .equ	COM1B1	= 5	; Compare Output Mode 1B, bit 1
                                 .equ	COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
                                 .equ	COM1A1	= 7	; Compare Output Mode 1A, bit 1
                                 
                                 ; TCCR1B - Timer/Counter1 Control Register B
                                 .equ	CS10	= 0	; Clock Select bit 0
                                 .equ	CS11	= 1	; Clock Select 1 bit 1
                                 .equ	CS12	= 2	; Clock Select1 bit 2
                                 .equ	WGM12	= 3	; Waveform Generation Mode Bit 2
                                 .equ	CTC1	= WGM12	; For compatibility
                                 .equ	WGM13	= 4	; Waveform Generation Mode Bit 3
                                 .equ	ICES1	= 6	; Input Capture 1 Edge Select
                                 .equ	ICNC1	= 7	; Input Capture 1 Noise Canceler
                                 
                                 ; TCCR1C - Timer/Counter1 Control Register C
                                 .equ	FOC1B	= 6	; Force Output Compare for Channel B
                                 .equ	FOC1A	= 7	; Force Output Compare for Channel A
                                 
                                 
                                 ; ***** CPU **************************
                                 ; SREG - Status Register
                                 .equ	SREG_C	= 0	; Carry Flag
                                 .equ	SREG_Z	= 1	; Zero Flag
                                 .equ	SREG_N	= 2	; Negative Flag
                                 .equ	SREG_V	= 3	; Two's Complement Overflow Flag
                                 .equ	SREG_S	= 4	; Sign Bit
                                 .equ	SREG_H	= 5	; Half Carry Flag
                                 .equ	SREG_T	= 6	; Bit Copy Storage
                                 .equ	SREG_I	= 7	; Global Interrupt Enable
                                 
                                 ; SPL - Stack Pointer Low
                                 .equ	SP0	= 0	; Stack pointer bit 0
                                 .equ	SP1	= 1	; Stack pointer bit 1
                                 .equ	SP2	= 2	; Stack pointer bit 2
                                 .equ	SP3	= 3	; Stack pointer bit 3
                                 .equ	SP4	= 4	; Stack pointer bit 4
                                 .equ	SP5	= 5	; Stack pointer bit 5
                                 .equ	SP6	= 6	; Stack pointer bit 6
                                 .equ	SP7	= 7	; Stack pointer bit 7
                                 
                                 ; MCUCR - MCU Control Register
                                 .equ BODSE = 2 ; BOD Sleep Enable
                                 .equ	SM0	= 3	; Sleep Mode Select Bit 0
                                 .equ	SM1	= 4	; Sleep Mode Select Bit 1
                                 .equ	SE	= 5	; Sleep Enable
                                 .equ	PUD	= 6	; 
                                 .equ BODS = 7 ; BOD Sleep
                                 
                                 ; MCUSR - MCU Status Register
                                 .equ	PORF	= 0	; Power-on reset flag
                                 .equ	EXTRF	= 1	; External Reset Flag
                                 .equ	BORF	= 2	; Brown-out Reset Flag
                                 .equ	WDRF	= 3	; Watchdog Reset Flag
                                 
                                 ; OSCCAL - Oscillator Calibration Value
                                 .equ	CAL0	= 0	; Oscillator Calibration Value Bit0
                                 .equ	CAL1	= 1	; Oscillator Calibration Value Bit1
                                 .equ	CAL2	= 2	; Oscillator Calibration Value Bit2
                                 .equ	CAL3	= 3	; Oscillator Calibration Value Bit3
                                 .equ	CAL4	= 4	; Oscillator Calibration Value Bit4
                                 .equ	CAL5	= 5	; Oscillator Calibration Value Bit5
                                 .equ	CAL6	= 6	; Oscillator Calibration Value Bit6
                                 .equ	CAL7	= 7	; Oscillator Calibration Value Bit7
                                 
                                 ; GPIOR2 - General Purpose I/O Register 2
                                 .equ	GPIOR20	= 0	; 
                                 .equ	GPIOR21	= 1	; 
                                 .equ	GPIOR22	= 2	; 
                                 .equ	GPIOR23	= 3	; 
                                 .equ	GPIOR24	= 4	; 
                                 .equ	GPIOR25	= 5	; 
                                 .equ	GPIOR26	= 6	; 
                                 .equ	GPIOR27	= 7	; 
                                 
                                 ; GPIOR1 - General Purpose I/O Register 1
                                 .equ	GPIOR10	= 0	; 
                                 .equ	GPIOR11	= 1	; 
                                 .equ	GPIOR12	= 2	; 
                                 .equ	GPIOR13	= 3	; 
                                 .equ	GPIOR14	= 4	; 
                                 .equ	GPIOR15	= 5	; 
                                 .equ	GPIOR16	= 6	; 
                                 .equ	GPIOR17	= 7	; 
                                 
                                 ; GPIOR0 - General Purpose I/O Register 0
                                 .equ	GPIOR00	= 0	; 
                                 .equ	GPIOR01	= 1	; 
                                 .equ	GPIOR02	= 2	; 
                                 .equ	GPIOR03	= 3	; 
                                 .equ	GPIOR04	= 4	; 
                                 .equ	GPIOR05	= 5	; 
                                 .equ	GPIOR06	= 6	; 
                                 .equ	GPIOR07	= 7	; 
                                 
                                 ; PRR - Power Reduction Register
                                 .equ	PRADC	= 0	; Power Reduction ADC
                                 .equ	PRUSI	= 1	; Power Reduction USI
                                 .equ	PRTIM0	= 2	; Power Reduction Timer/Counter0
                                 .equ	PRTIM1	= 3	; Power Reduction Timer/Counter1
                                 
                                 ; CLKPR - Clock Prescale Register
                                 .equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
                                 .equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
                                 .equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
                                 .equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
                                 .equ	CLKPCE	= 7	; Clock Prescaler Change Enable
                                 
                                 
                                 ; ***** BOOT_LOAD ********************
                                 ; SPMCSR - Store Program Memory Control Register
                                 .equ	SPMEN	= 0	; Store Program Memory Enable
                                 .equ	PGERS	= 1	; Page Erase
                                 .equ	PGWRT	= 2	; Page Write
                                 .equ	RFLB	= 3	; Read fuse and lock bits
                                 .equ	CTPB	= 4	; Clear temporary page buffer
                                 
                                 
                                 
                                 ; ***** LOCKSBITS ********************************************************
                                 .equ	LB1	= 0	; Lockbit
                                 .equ	LB2	= 1	; Lockbit
                                 
                                 
                                 ; ***** FUSES ************************************************************
                                 ; LOW fuse bits
                                 .equ	CKSEL0	= 0	; Select Clock source
                                 .equ	CKSEL1	= 1	; Select Clock source
                                 .equ	CKSEL2	= 2	; Select Clock source
                                 .equ	CKSEL3	= 3	; Select Clock source
                                 .equ	SUT0	= 4	; Select start-up time
                                 .equ	SUT1	= 5	; Select start-up time
                                 .equ	CKOUT	= 6	; Clock Output Enable
                                 .equ	CKDIV8	= 7	; Divide clock by 8
                                 
                                 ; HIGH fuse bits
                                 .equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
                                 .equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
                                 .equ	BODLEVEL2	= 2	; Brown-out Detector trigger level
                                 .equ	EESAVE	= 3	; EEPROM memory is preserved through the Chip Erase
                                 .equ	WDTON	= 4	; Watchdog Timer always on
                                 .equ	SPIEN	= 5	; Enable Serial Program and Data Downloading
                                 .equ	DWEN	= 6	; DebugWIRE Enable
                                 .equ	RSTDISBL	= 7	; External Reset disable
                                 
                                 ; EXTENDED fuse bits
                                 .equ	SELFPRGEN	= 0	; Self-Programming Enable
                                 
                                 
                                 
                                 ; ***** CPU REGISTER DEFINITIONS *****************************************
                                 .def	XH	= r27
                                 .def	XL	= r26
                                 .def	YH	= r29
                                 .def	YL	= r28
                                 .def	ZH	= r31
                                 .def	ZL	= r30
                                 
                                 
                                 
                                 ; ***** DATA MEMORY DECLARATIONS *****************************************
                                 .equ	FLASHEND	= 0x03ff	; Note: Word address
                                 .equ	IOEND	= 0x003f
                                 .equ	SRAM_START	= 0x0060
                                 .equ	SRAM_SIZE	= 128
                                 .equ	RAMEND	= 0x00df
                                 .equ	XRAMEND	= 0x0000
                                 .equ	E2END	= 0x007f
                                 .equ	EEPROMEND	= 0x007f
                                 .equ	EEADRBITS	= 7
                                 #pragma AVRPART MEMORY PROG_FLASH 2048
                                 #pragma AVRPART MEMORY EEPROM 128
                                 #pragma AVRPART MEMORY INT_SRAM SIZE 128
                                 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
                                 
                                 
                                 
                                 ; ***** BOOTLOADER DECLARATIONS ******************************************
                                 .equ	NRWW_START_ADDR	= 0x0
                                 .equ	NRWW_STOP_ADDR	= 0x3ff
                                 .equ	RWW_START_ADDR	= 0x0
                                 .equ	RWW_STOP_ADDR	= 0x0
                                 .equ	PAGESIZE	= 16
                                 
                                 
                                 
                                 ; ***** INTERRUPT VECTORS ************************************************
                                 .equ	EXT_INT0addr	= 0x0001	; External Interrupt Request 0
                                 .equ	PCI0addr	= 0x0002	; Pin Change Interrupt Request 0
                                 .equ	PCI1addr	= 0x0003	; Pin Change Interrupt Request 1
                                 .equ	WATCHDOGaddr	= 0x0004	; Watchdog Time-out
                                 .equ	ICP1addr	= 0x0005	; Timer/Counter1 Capture Event
                                 .equ	OC1Aaddr	= 0x0006	; Timer/Counter1 Compare Match A
                                 .equ	OC1Baddr	= 0x0007	; Timer/Counter1 Compare Match B
                                 .equ	OVF1addr	= 0x0008	; Timer/Counter1 Overflow
                                 .equ	OC0Aaddr	= 0x0009	; Timer/Counter0 Compare Match A
                                 .equ	OC0Baddr	= 0x000a	; Timer/Counter0 Compare Match B
                                 .equ	OVF0addr	= 0x000b	; Timer/Counter0 Overflow
                                 .equ	ACIaddr	= 0x000c	; Analog Comparator
                                 .equ	ADCCaddr	= 0x000d	; ADC Conversion Complete
                                 .equ	ERDYaddr	= 0x000e	; EEPROM Ready
                                 .equ	USI_STRaddr	= 0x000f	; USI START
                                 .equ	USI_OVFaddr	= 0x0010	; USI Overflow
                                 
                                 .equ	INT_VECTORS_SIZE	= 17	; size in words
                                 
                                 #endif  /* _TN24ADEF_INC_ */
                                 
                                 ; ***** END OF FILE ******************************************************
                                 .list                       ; Enable listing
                                 
                                 ;
                                 ; Registers
                                 .def seq_length_r = r10			; Current length of sequence
                                 .def temp_r = r16           ; Temp general register A
                                 .def temp_r_b = r23					; Temp general register B
                                 .def temp_r_c = r26					; Temp general register C
                                 .def mcu_state_r = r17      ; Current state of MCU. This register will be compared in an main loop
                                 .def delay_counter_r = r19  ; Register for storing delay counter
                                 .def poll_step_r = r20			; Current poll step for checking the input with answer
                                 
                                 ;
                                 ; LEDS constants
                                 .equ LED_DIR = DDRA     
                                 .equ LED_PORT = PORTA   
                                 .equ LED_PIN = PINA   
                                 .equ LED_PIN_0 = PINA0      
                                 .equ LED_PIN_1 = PINA1      
                                 .equ LED_PIN_2 = PINA2     
                                 .equ LED_PIN_3 = PINA3      
                                 
                                 ;
                                 ; Buttons constants
                                 .equ SW_DIR = DDRA
                                 .equ SW_PORT = PORTA
                                 .equ SW_PIN = PINA
                                 .equ SW_PIN_4 = PINA4
                                 .equ SW_PIN_5 = PINA5
                                 .equ SW_PIN_6 = PINA6
                                 .equ SW_PIN_7 = PINA7
                                 
                                 ;
                                 ; Buzzer constants
                                 .equ BUZZ_DIR = DDRB
                                 .equ BUZZ_PORT = PORTB
                                 .equ BUZZ_PIN = PINB2
                                 
                                 ;
                                 ; States constants
                                 .equ INIT_STATE = 0x01
                                 .equ SHOWING_STATE = 0x02
                                 .equ POLLING_STATE = 0x03
                                 
                                 ;
                                 ; SW Flags states constants
                                 .equ SW_FLAG_1 = 0xe0
                                 .equ SW_FLAG_2 = 0xd0
                                 .equ SW_FLAG_3 = 0xb0
                                 .equ SW_FLAG_4 = 0x70
                                 
                                 .equ SEQ_LENGTH = 2
                                 
                                 ; Value that stored in OCR0A for each tone
                                 ; 880Hz = 71
                                 ; 785Hz = 80
                                 ; 590Hz = 105
                                 ; 440Hz = 142
                                 
                                 .include "macros.asm"       ; Include macros
                                 
                                 ; Initialize stack pointer
                                 ; @0 - Temp register
                                 .macro init_stack_p
                                   ldi @0, low(@1)
                                   out SPL, @0
                                   clr @0
                                   .ifdef SPH 
                                 	ldi @0, high(RAMEND) 
                                 	out SPH, @0 
                                 	clr @0
                                   .endif
                                 .endm
                                 
                                 ;
                                 ; out immediate
                                 ; @0 - I/O Register
                                 ; @1 - Data to write
                                 .macro outi
                                 	push temp_r
                                   ldi temp_r, @1
                                   out @0, temp_r
                                   pop temp_r
                                 .endm
                                 
                                 ;
                                 ; sts immediate
                                 ; @0 - SRAM Address
                                 ; @1 - Data to write
                                 .macro stsi
                                   push temp_r
                                   ldi temp_r, @1
                                   sts @0, temp_r
                                   pop temp_r
                                 .endm
                                 
                                 ;
                                 ; Set MCU global state
                                 ; @0 - New state
                                 .macro set_state
                                   sts PREVIOUS_STATE_ADDRESS, mcu_state_r         ; Write previous state to SRAM
                                   stsi CURRENT_STATE_ADDRESS, @0
                                 .endm
                                 
                                 .macro buzzer_on
                                   sbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 .macro buzzer_off
                                   cbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 .macro beep_led_1
                                   outi OCR0A, 142
                                   sbi LED_PORT, 0
                                   sbi BUZZ_DIR, BUZZ_PIN
                                   rcall delay
                                   cbi LED_PORT, 0
                                   cbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 .macro beep_led_2
                                   outi OCR0A, 71
                                   sbi LED_PORT, 1
                                   sbi BUZZ_DIR, BUZZ_PIN
                                   rcall delay
                                   cbi LED_PORT, 1
                                   cbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 .macro beep_led_3
                                   outi OCR0A, 105
                                   sbi LED_PORT, 2
                                   sbi BUZZ_DIR, BUZZ_PIN
                                   rcall delay
                                   cbi LED_PORT, 2
                                   cbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 .macro beep_led_4
                                   outi OCR0A, 80
                                   sbi LED_PORT, 3
                                   sbi BUZZ_DIR, BUZZ_PIN
                                   rcall delay
                                   cbi LED_PORT, 3
                                   cbi BUZZ_DIR, BUZZ_PIN
                                 .endm
                                 
                                 
                                 
                                 
                                 .dseg                       ; Data segment
                                 .org	SRAM_START
                                 
                                 ;
                                 ; MCU Global states addresses
000060                           CURRENT_STATE_ADDRESS:  		.byte	0x01
000061                           PREVIOUS_STATE_ADDRESS: 		.byte 0x01
                                 
                                 ;
                                 ; Button flags
000062                           SW_FLAGS_ADDRESS: 					.byte 0x01
                                 
                                 .cseg                       ; Code segment
                                 .org 0x00
                                 
                                 ;
                                 ; Setup vectors
000000 c03e                      rjmp start                  ; Program start at RESET vector
000001 9518                      reti                        ; External Interrupt Request 0 / inactive
000002 c00e                      rjmp PCINT0_vect            ; Pin Change Interrupt Request 0 / active
000003 9518                      reti                        ; Pin Change Interrupt Request 1 / inactive
000004 9518                      reti                        ; Watchdog Time-out / inactive
000005 9518                      reti                        ; Timer/Counter1 Capture Event / inactive
000006 9518                      reti                        ; Timer/Counter1 Compare Match A / inactive
000007 9518                      reti                        ; Timer/Counter1 Compare Match B / inactive
000008 9518                      reti                        ; Timer/Counter1 Overflow / inactive
000009 9518                      reti												; Timer/Counter0 Compare Match A / inactive
00000a 9518                      reti                        ; Timer/Counter0 Compare Match B / inactive
00000b c015                      rjmp TIM0_OVF_vect					; Timer/Counter0 Overflow / active
00000c 9518                      reti                        ; Analog Comparator / inactive
00000d 9518                      reti                        ; ADC Conversion Complete / inactive
00000e 9518                      reti                        ; EEPROM Ready / inactive
00000f 9518                      reti                        ; USI START / inactive
000010 9518                      reti                        ; USI Overflow / inactive
                                 
                                 ;
                                 ; Interrupt service routines
                                 PCINT0_vect:								; Button handler
000011 931f                        push r17
000012 932f                        push r18
000013 b72f                        in r18, SREG              ; Save status register
000014 9110 0060                   lds mcu_state_r, CURRENT_STATE_ADDRESS      
000016 3013                        cpi mcu_state_r, POLLING_STATE
000017 f431                        brne quit                 ; Do not change button flags unless in POLLING state of mcu
000018 b319                        in r17, PINA              ; Load current pins status of PINA
000019 7f10                        andi r17, 0xf0            ; Get pins status of only buttons
00001a d193                        rcall delay_20ms          ; Delay for button
00001b 9310 0062                   sts SW_FLAGS_ADDRESS, r17 ; Update flag status in SRAM
00001d bf2f                        out SREG, r18
                                 
                                   quit:
00001e 912f                        pop r18
00001f 911f                        pop r17
000020 9518                      reti
                                 
                                 TIM0_OVF_vect:									; Random byte generator
000021 937f                      	push temp_r_b
000022 b77f                      	in temp_r_b, SREG
                                 	
000023 c002                      	rjmp gen_start
                                   
000024 ea08                        ldi temp_r, 168
000025 b752                        in r21, TCNT0
                                   
                                   gen_start:
000026 2705                      	  eor temp_r, r21
000027 9502                      	  swap temp_r
000028 0f50                      	  add r21, temp_r
000029 bf7f                      	out SREG, temp_r_b
00002a 917f                      	pop temp_r_b
00002b 9518                      reti
                                 
                                 MCU_Init:										; This function executes once on start the main program
00002c d16c                        rcall init_ports
00002d d15b                        rcall init_interrupts
00002e d160                        rcall init_buzzer
                                   
                                   ;
                                   ; Init important registers for game
00002f ef3f                        ldi delay_counter_r, 0xff
000030 e041                        ldi poll_step_r, 1
000031 e0a2                        ldi temp_r_c, SEQ_LENGTH
000032 2eaa                        mov seq_length_r, temp_r_c
000033 27ff                        clr ZH
000034 e8e0                        ldi ZL, $80
                                   
000035 d002                        rcall MCU_Delay					; Wait 1 sec before start main program
                                    
000036 9478                        sei                       ; Enable Global Interrupts
000037 9508                      ret
                                 
                                 MCU_Delay:
000038 e073                      	ldi temp_r_b, 3
                                   _init_loop_loading:
000039 d0fd                          rcall effect_1
00003a 957a                          dec temp_r_b
00003b f7e9                          brne _init_loop_loading
00003c d188                        rcall delay_1s
00003d 2777                        clr temp_r_b
00003e 9508                      ret
                                   
                                 ;
                                 ; Program start at reset
                                 start:
00003f ed0f
000040 bf0d
000041 2700                        init_stack_p temp_r, RAMEND
                                 
000042 9310 0061
000044 930f
000045 e001
000046 9300 0060
000048 910f                        set_state INIT_STATE
                                 loop:                       ; Program loop
000049 9110 0060                   lds mcu_state_r, CURRENT_STATE_ADDRESS
                                   init:                     ; Init state
00004b 3011                          cpi mcu_state_r, INIT_STATE
00004c f441                          brne showing
00004d dfde                          rcall MCU_Init
00004e 9310 0061
000050 930f
000051 e002
000052 9300 0060
000054 910f                          set_state SHOWING_STATE
                                   showing:                  ; Showing state
000055 3012                          cpi mcu_state_r, SHOWING_STATE
000056 f441                          brne polling
000057 d093                          rcall show_sequence	    ; Generate sequence and save answer to SRAM
000058 9310 0061
00005a 930f
00005b e003
00005c 9300 0060
00005e 910f                          set_state POLLING_STATE
                                   polling:                  ; Polling state
00005f 3013                          cpi mcu_state_r, POLLING_STATE
000060 f5c1                          brne default
                                     btn_1:
000061 9120 0062                       lds r18, SW_FLAGS_ADDRESS
000063 3e20                            cpi r18, SW_FLAG_1
000064 f451                            brne btn_2						; Check next button
                                       led_on_1:
000065 930f
000066 e80e
000067 bf06
000068 910f                              outi OCR0A, 142
000069 9ad8                              sbi LED_PORT, 0
00006a 9aba                              sbi BUZZ_DIR, BUZZ_PIN
00006b d02f                              rcall btn_handler    
00006c 98d8                              cbi LED_PORT, 0
00006d 98ba                        			cbi BUZZ_DIR, BUZZ_PIN
00006e cff2                              rjmp btn_1
                                     btn_2:
00006f 9120 0062                       lds r18, SW_FLAGS_ADDRESS
000071 3d20                            cpi r18, SW_FLAG_2
000072 f451                            brne btn_3
                                       led_on_2:
000073 930f
000074 e407
000075 bf06
000076 910f                              outi OCR0A, 71
000077 9ad9                              sbi LED_PORT, 1
000078 9aba                              sbi BUZZ_DIR, BUZZ_PIN
000079 d021                              rcall btn_handler
00007a 98d9                              cbi LED_PORT, 1
00007b 98ba                        			cbi BUZZ_DIR, BUZZ_PIN
00007c cff2                              rjmp btn_2
                                     btn_3:
00007d 9120 0062                       lds r18, SW_FLAGS_ADDRESS
00007f 3b20                            cpi r18, SW_FLAG_3
000080 f451                            brne btn_4
                                       led_on_3:
000081 930f
000082 e609
000083 bf06
000084 910f                              outi OCR0A, 105
000085 9ada                              sbi LED_PORT, 2
000086 9aba                              sbi BUZZ_DIR, BUZZ_PIN
000087 d013                              rcall btn_handler
000088 98da                              cbi LED_PORT, 2
000089 98ba                        			cbi BUZZ_DIR, BUZZ_PIN
00008a cff2                              rjmp btn_3
                                     btn_4:
00008b 9120 0062                       lds r18, SW_FLAGS_ADDRESS
00008d 3720                            cpi r18, SW_FLAG_4
00008e f451                            brne default
                                       led_on_4:
00008f 930f
000090 e500
000091 bf06
000092 910f                              outi OCR0A, 80
000093 9adb                              sbi LED_PORT, 3
000094 9aba                              sbi BUZZ_DIR, BUZZ_PIN
000095 d005                              rcall btn_handler
000096 98db                              cbi LED_PORT, 3
000097 98ba                        			cbi BUZZ_DIR, BUZZ_PIN
000098 cff2                              rjmp btn_4
                                   default:									
000099 d092                        	rcall OCR0A_reset
00009a cfae                      rjmp loop
                                 
                                 
                                 btn_handler:								; Check the input value with answer in SRAM
00009b 932f                      	push r18
00009c d11c                      	rcall delay_50ms
00009d d11b                        rcall delay_50ms
00009e d11a                        rcall delay_50ms
00009f b3a9                        in temp_r_c, PINA
0000a0 2f9a                        mov r25, temp_r_c           
0000a1 7fa0                      	andi temp_r_c, 0xf0
0000a2 709f                      	andi r25, 0x0f
0000a3 27aa                      	clr temp_r_c
0000a4 93a0 0062                 	sts SW_FLAGS_ADDRESS, temp_r_c 
                                 	
0000a6 9181                      	ld r24, Z+
0000a7 1798                      	cp r25, r24							; Check answer
0000a8 f429                      	brne _game_over					; Game over
                                 	
0000a9 2d2a                      	mov r18, seq_length_r
0000aa 1724                      	cp r18, poll_step_r
0000ab f051                      	breq _btn_handler_exit_state
                                 	
0000ac 9543                      	inc poll_step_r
                                   
0000ad c010                      	rjmp _btn_handler_exit
                                 	
                                 	_game_over:
0000ae 912f                          pop r18
0000af d087                      		rcall effect_1
0000b0 ef3f                      		ldi delay_counter_r, 0xff
0000b1 e0a2                      		ldi temp_r_c, SEQ_LENGTH
0000b2 95aa                      		dec temp_r_c
0000b3 2eaa                        	mov seq_length_r, temp_r_c
0000b4 d00c                          rcall reset_game
0000b5 9508                          ret
                                 	
                                 	_btn_handler_exit_state:
0000b6 912f                      		pop r18
0000b7 ef00                          ldi temp_r, 0xf0
0000b8 bb0b                          out LED_PORT, temp_r
0000b9 98ba                          cbi BUZZ_DIR, BUZZ_PIN
0000ba d0fe                          rcall delay_50ms
0000bb d0a4                          rcall effect_2
0000bc d004                      		rcall reset_game
0000bd 9508                      		ret
                                 	_btn_handler_exit:
0000be 912f                      		pop r18
0000bf 9508                      		ret
0000c0 9508                      ret
                                 
                                 reset_game:
0000c1 27ff                        clr ZH
0000c2 e8e0                        ldi ZL, $80
0000c3 98ba                        cbi BUZZ_DIR, BUZZ_PIN
0000c4 ef00                        ldi temp_r, 0xf0
0000c5 bb0b                        out LED_PORT, temp_r
0000c6 d0fe                        rcall delay_1s
0000c7 9310 0061
0000c9 930f
0000ca e002
0000cb 9300 0060
0000cd 910f                        set_state SHOWING_STATE
0000ce e041                        ldi poll_step_r, 1
0000cf 94a3                        inc seq_length_r
0000d0 9508                      ret
                                 
                                 gen_ran_seq:								; Generate random sequence of bytes for leds and save answer to SRAM
0000d1 2d7a                      	mov temp_r_b, seq_length_r
0000d2 27dd                      	clr YH
0000d3 e8c0                      	ldi YL, $80
                                 	_gen_ran_loop:
0000d4 d0e4                      		rcall delay_50ms				; Delay is required!
0000d5 2f65                      		mov r22, r21
                                 		
0000d6 3466                      		cpi r22, 70
0000d7 f030                      	  brlo _gen_answ_1
                                 	
0000d8 386c                      	  cpi r22, 140
0000d9 f030                      	  brlo _gen_answ_2
                                 	  
0000da 3c68                      	  cpi r22, 200
0000db f030                      	  brlo _gen_answ_3
                                 	  
0000dc 3f6f                      	  cpi r22, 255
0000dd f030                      	  brlo _gen_answ_4
                                 	  
                                 	  _gen_answ_1:
0000de e0a1                      	  	ldi temp_r_c, 0x01
0000df c005                      	  	rjmp _gen_ran_write
                                 	  _gen_answ_2:
0000e0 e0a2                      	  	ldi temp_r_c, 0x02
0000e1 c003                      	  	rjmp _gen_ran_write
                                 	  _gen_answ_3:
0000e2 e0a4                      	  	ldi temp_r_c, 0x04
0000e3 c001                      	  	rjmp _gen_ran_write
                                 	  _gen_answ_4:
0000e4 e0a8                      	  	ldi temp_r_c, 0x08
                                 	  _gen_ran_write:
0000e5 93a9                      			st Y+, temp_r_c
0000e6 957a                      			dec temp_r_b
0000e7 3070                      			cpi temp_r_b, 0
0000e8 f759                      			brne _gen_ran_loop
0000e9 0000                      	  nop
0000ea 9508                      ret
                                 
                                 show_sequence:
0000eb dfe5                      	rcall gen_ran_seq					; Answer stored in SRAM in addr $80:{SEQ_LENGTH}
                                 	show_start:
0000ec 2d7a                      	mov temp_r_b, seq_length_r
                                 
0000ed 27dd                      	clr YH
0000ee e8c0                      	ldi YL, $80
                                 	
                                 	_sequence_loop:
0000ef 3070                      		cpi temp_r_b, 0
0000f0 f1c1                      		breq _seq_quit
                                 		
0000f1 91a9                      		ld temp_r_c, Y+
0000f2 30a1                      		cpi temp_r_c, 0x01
0000f3 f031                      		breq beep_1
                                 		
0000f4 30a2                      		cpi temp_r_c, 0x02
0000f5 f079                      		breq beep_2
                                 		
0000f6 30a4                      		cpi temp_r_c, 0x04
0000f7 f0c1                      		breq beep_3
                                 		
0000f8 30a8                      		cpi temp_r_c, 0x08
0000f9 f109                      		breq beep_4
                                 		
                                 		beep_1:
0000fa 930f
0000fb e80e
0000fc bf06
0000fd 910f
0000fe 9ad8
0000ff 9aba
000100 d09f
000101 98d8
000102 98ba                          	beep_led_1
000103 d028                          	rcall OCR0A_reset
000104 c020                          	rjmp beep_quit
                                 	  beep_2:
000105 930f
000106 e407
000107 bf06
000108 910f
000109 9ad9
00010a 9aba
00010b d094
00010c 98d9
00010d 98ba                      	    beep_led_2
00010e d01d                      	    rcall OCR0A_reset
00010f c015                      	    rjmp beep_quit
                                 	  beep_3:
000110 930f
000111 e609
000112 bf06
000113 910f
000114 9ada
000115 9aba
000116 d089
000117 98da
000118 98ba                      	    beep_led_3
000119 d012                      	    rcall OCR0A_reset
00011a c00a                      	    rjmp beep_quit
                                 	  beep_4:
00011b 930f
00011c e500
00011d bf06
00011e 910f
00011f 9adb
000120 9aba
000121 d07e
000122 98db
000123 98ba                      	    beep_led_4
000124 d007                      	    rcall OCR0A_reset
                                 	  beep_quit:
000125 d07a                      	    rcall delay
000126 957a                      	    dec temp_r_b
000127 3070                      	    cpi temp_r_b, 0
000128 f631                      	    brne _sequence_loop
                                 
                                   _seq_quit:
000129 d007                        rcall dec_delay_counter
00012a d08e                        rcall delay_50ms
00012b 9508                      ret
                                 
                                 OCR0A_reset:								; This function need to set the OCR0A register to 0xff for overflow interrupt
00012c 937f                      	push temp_r_b
00012d ef7f                      	ldi temp_r_b, 0xff
00012e bf76                      	out OCR0A, temp_r_b
00012f 917f                      	pop temp_r_b
000130 9508                      ret
                                 
                                 dec_delay_counter:
000131 503a                        subi delay_counter_r, 10
000132 3238                        cpi delay_counter_r, 40
000133 f008                        brlo _reset_counter
000134 9508                        ret
                                   _reset_counter:
000135 ef3f                          ldi delay_counter_r, 0xff
000136 9508                      ret
                                 
                                 effect_1:                   ; Shift bits of an leds in port every 50ms
000137 931f                      	push r17
000138 932f                      	push r18
000139 933f                      	push r19
00013a 934f                      	push r20
00013b 94f8                      	cli
00013c b34b                        in r20, LED_PORT
                                 
00013d 930f
00013e ef01
00013f bb0b
000140 910f                        outi LED_PORT, 0xf1
000141 d077                        rcall delay_50ms
000142 e011                        ldi r17, 0x01
000143 e033                        ldi r19, 3
                                   _eff_1_shift_l:            ; Shift bits to left loop
000144 ef20                          ldi r18, 0xf0
000145 0f11                          lsl r17
000146 0f21                          add r18, r17
000147 bb2b                          out LED_PORT, r18
000148 d070                          rcall delay_50ms
000149 953a                          dec r19
00014a f7c9                          brne _eff_1_shift_l
                                 
00014b 930f
00014c ef08
00014d bb0b
00014e 910f                        outi LED_PORT, 0xf8
00014f d069                        rcall delay_50ms
000150 e018                        ldi r17, 0x08
000151 e033                        ldi r19, 3
                                   _eff_1_shift_r:            ; Shift bits to right loop
000152 ef20                          ldi r18, 0xf0
000153 9516                          lsr r17
000154 0f21                          add r18, r17
000155 bb2b                          out LED_PORT, r18
000156 d062                          rcall delay_50ms
000157 953a                          dec r19
000158 f7c9                          brne _eff_1_shift_r
                                 
000159 9478                        sei
                                   ; Out saved PORT values
00015a bb4b                        out LED_PORT, r20
00015b 914f                        pop r20
00015c 913f                        pop r19
00015d 912f                        pop r18
00015e 911f                        pop r17
00015f 9508                      ret
                                 
                                 effect_2:
000160 930f
000161 e80e
000162 bf06
000163 910f                        outi OCR0A, 142
000164 9ad8                        sbi LED_PORT, 0
000165 9aba                        sbi BUZZ_DIR, BUZZ_PIN
000166 d052                        rcall delay_50ms
000167 d051                        rcall delay_50ms
000168 98d8                        cbi LED_PORT, 0
000169 98ba                        cbi BUZZ_DIR, BUZZ_PIN
                                 
00016a 930f
00016b e609
00016c bf06
00016d 910f                        outi OCR0A, 105
00016e 9ad9                        sbi LED_PORT, 1
00016f 9aba                        sbi BUZZ_DIR, BUZZ_PIN
000170 d048                        rcall delay_50ms
000171 d047                        rcall delay_50ms
000172 98d9                        cbi LED_PORT, 1
000173 98ba                        cbi BUZZ_DIR, BUZZ_PIN
                                 
000174 930f
000175 e500
000176 bf06
000177 910f                        outi OCR0A, 80
000178 9ada                        sbi LED_PORT, 2
000179 9aba                        sbi BUZZ_DIR, BUZZ_PIN
00017a d03e                        rcall delay_50ms
00017b d03d                        rcall delay_50ms
00017c 98da                        cbi LED_PORT, 2
00017d 98ba                        cbi BUZZ_DIR, BUZZ_PIN
                                 
00017e 930f
00017f e407
000180 bf06
000181 910f                        outi OCR0A, 71
000182 9adb                        sbi LED_PORT, 3
000183 9aba                        sbi BUZZ_DIR, BUZZ_PIN
000184 d034                        rcall delay_50ms
000185 d033                        rcall delay_50ms
000186 98db                        cbi LED_PORT, 3
000187 98ba                        cbi BUZZ_DIR, BUZZ_PIN
000188 9508                      ret
                                 
                                 init_interrupts:
                                   ;
                                   ; Enable Port Change Interrupt
000189 e100                        ldi temp_r, (1<<PCIE0)
00018a bf0b                        out GIMSK, temp_r
                                 
                                   ;
                                   ; Set Pin Change Mask Register
00018b ef00                        ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7)
00018c bb02                        out PCMSK0, temp_r
                                 
00018d 2700                        clr temp_r
00018e 9508                      ret
                                 
                                 init_buzzer:
00018f 98ba                        cbi BUZZ_DIR, BUZZ_PIN
                                   
                                   ; Setup timer
000190 e402                        ldi temp_r, (1<<COM0A0) | (1<<WGM01)        ; Set CTC timer mode and toggle OC0A pin on Compare Match
000191 bf00                        out TCCR0A, temp_r
                                 
000192 ef0f                        ldi temp_r, 255
000193 bf06                        out OCR0A, temp_r
                                 
000194 e002                        ldi temp_r, (1<<CS01)                       ; Prescale on 8
000195 bf03                        out TCCR0B, temp_r
                                   
000196 e001                        ldi temp_r, (1<<TOIE0)											; Enable Timer/Counter0 Overflow Interrupt
000197 bf09                        out TIMSK0, temp_r
000198 9508                      ret
                                 
                                 init_ports:                 	; Init MCU ports 
000199 e00f                        ldi temp_r, 0x0f						; Setup PORTA
00019a bb0a                        out DDRA, temp_r            ; Set directions of leds and buttons
00019b 9502                        swap temp_r
00019c bb0b                        out PORTA, temp_r						; Set low signal on leds and pull-up on buttons
                                 
                                   ; Setup PORTB
00019d 9aba                        sbi DDRB, BUZZ_PIN        	; Set direction of buzzer pin to output
00019e 98c2                        cbi PORTB, BUZZ_PIN       	; Set low signal on buzzer
00019f 9508                      ret
                                 
                                 delay:                      	; For 1MHz frequency
0001a0 932f                        push r18
0001a1 934f                        push r20
0001a2 ef2f                        ldi r18, 255
0001a3 2f43                        mov r20, delay_counter_r
                                   _delay_loop:
0001a4 0000                          nop
0001a5 952a                          dec r18
0001a6 f7e9                          brne _delay_loop
0001a7 0000                          nop
0001a8 954a                          dec r20
0001a9 f7d1                          brne _delay_loop
0001aa 0000                          nop
0001ab 914f                        pop r20
0001ac 912f                        pop r18
0001ad 9508                      ret
                                 
                                 delay_20ms:
0001ae 932f                        push r18
0001af 933f                        push r19
                                 
0001b0 e12a                        ldi r18, 26  
0001b1 ef39                        ldi r19, 249   
                                     _loop_d_20ms: 
0001b2 953a                            dec  r19          
0001b3 f7f1                            brne _loop_d_20ms 
0001b4 952a                            dec  r18          
0001b5 f7e1                            brne _loop_d_20ms 
0001b6 913f                        pop r19
0001b7 912f                        pop r18
0001b8 9508                      ret
                                 
                                 delay_50ms:                 	; For 1MHz frequency
0001b9 932f                        push r18
0001ba 933f                        push r19
                                 
0001bb e421                        ldi r18, 65    
0001bc ee3f                        ldi r19, 239   
                                     _loop_d_50ms: 
0001bd 953a                            dec  r19          
0001be f7f1                            brne _loop_d_50ms 
0001bf 952a                            dec  r18          
0001c0 f7e1                            brne _loop_d_50ms 
0001c1 0000                            nop 
0001c2 913f                        pop r19
0001c3 912f                        pop r18              
0001c4 9508                      ret
                                 
                                 
                                 delay_1s:                   ; For 1MHz frequency 
0001c5 938f                      	push r24
0001c6 939f                      	push r25
                                   .equ outer_count = 100
                                   .equ inner_count = 2499
                                 
0001c7 e624                        ldi r18, outer_count       
                                 _reset:                   
0001c8 ec83                        ldi r24, low(inner_count)
0001c9 e099                        ldi r25, high(inner_count)
                                 _loop:                  
0001ca 9701                        sbiw r24, 1             
0001cb f7f1                        brne _loop             
0001cc 952a                        dec r18                 
0001cd f7d1                        brne _reset             
0001ce e624                        ldi r18, outer_count
0001cf 919f                      	pop r25
0001d0 918f                      	pop r24
0001d1 9508                      ret
                                 
0001d2 654d
0001d3 6f6d
0001d4 7972
0001d5 6c20
0001d6 6465
0001d7 6720
0001d8 6d61
0001d9 2e65
0001da 5720
0001db 6972
0001dc 7474
0001dd 6e65
0001de 6220
0001df 2079
0001e0 6553
0001e1 6772
0001e2 7965
0001e3 5920
0001e4 7261
0001e5 6f6b
0001e6 2076
0001e7 3732
0001e8 302e
0001e9 2e39
0001ea 3032


RESOURCE USE INFORMATION
------------------------

Notice:
The register and instruction counts are symbol table hit counts,
and hence implicitly used resources are not counted, eg, the
'lpm' instruction without operands implicitly uses r0 and z,
none of which are counted.

x,y,z are separate entities in the symbol table and are
counted separately from r26..r31 here.

.dseg memory usage only counts static data declared with .byte

"ATtiny24A" register use summary:
x  :   0 y  :   2 z  :   1 r0 :   0 r1 :   0 r2 :   0 r3 :   0 r4 :   0 
r5 :   0 r6 :   0 r7 :   0 r8 :   0 r9 :   0 r10:   6 r11:   0 r12:   0 
r13:   0 r14:   0 r15:   0 r16: 100 r17:  23 r18:  41 r19:  20 r20:  12 
r21:   4 r22:   5 r23:  18 r24:   6 r25:   6 r26:  20 r27:   0 r28:   2 
r29:   2 r30:   2 r31:   2 
Registers used: 18 out of 35 (51.4%)

"ATtiny24A" instruction use summary:
.lds  :   0 .sts  :   0 adc   :   0 add   :   3 adiw  :   0 and   :   0 
andi  :   3 asr   :   0 bclr  :   0 bld   :   0 brbc  :   0 brbs  :   0 
brcc  :   0 brcs  :   0 break :   0 breq  :   6 brge  :   0 brhc  :   0 
brhs  :   0 brid  :   0 brie  :   0 brlo  :   5 brlt  :   0 brmi  :   0 
brne  :  22 brpl  :   0 brsh  :   0 brtc  :   0 brts  :   0 brvc  :   0 
brvs  :   0 bset  :   0 bst   :   0 cbi   :  28 cbr   :   0 clc   :   0 
clh   :   0 cli   :   1 cln   :   0 clr   :   8 cls   :   0 clt   :   0 
clv   :   0 clz   :   0 com   :   0 cp    :   2 cpc   :   0 cpi   :  20 
cpse  :   0 dec   :  13 eor   :   1 icall :   0 ijmp  :   0 in    :   6 
inc   :   2 ld    :   2 ldd   :   0 ldi   :  61 lds   :   6 lpm   :   0 
lsl   :   1 lsr   :   1 mov   :   8 movw  :   0 neg   :   0 nop   :   5 
or    :   0 ori   :   0 out   :  31 pop   :  37 push  :  35 rcall :  48 
ret   :  21 reti  :  16 rjmp  :  16 rol   :   0 ror   :   0 sbc   :   0 
sbci  :   0 sbi   :  25 sbic  :   0 sbis  :   0 sbiw  :   1 sbr   :   0 
sbrc  :   0 sbrs  :   0 sec   :   0 seh   :   0 sei   :   2 sen   :   0 
ser   :   0 ses   :   0 set   :   0 sev   :   0 sez   :   0 sleep :   0 
spm   :   0 st    :   1 std   :   0 sts   :  10 sub   :   0 subi  :   1 
swap  :   2 tst   :   0 wdr   :   0 
Instructions used: 35 out of 105 (33.3%)

"ATtiny24A" memory use summary [bytes]:
Segment   Begin    End      Code   Data   Used    Size   Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x0003d8    932     52    984    2048  48.0%
[.dseg] 0x000060 0x000063      0      3      3     128   2.3%
[.eseg] 0x000000 0x000000      0      0      0     128   0.0%

Assembly complete, 0 errors, 1 warnings