mirror of
https://github.com/sergeyyarkov/attiny24a_memory-led-game.git
synced 2026-10-11 10:18:58 +03:00
1636 lines
88 KiB
Plaintext
1636 lines
88 KiB
Plaintext
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AVRASM ver. 2.2.7 firmware.asm Thu May 26 15:43:31 2022
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firmware.asm(13): Including file 'def.inc'
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firmware.asm(22): warning: Register r26 already defined by the .DEF directive
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firmware.asm(74): Including file 'macros.asm'
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firmware.asm(13): Including file 'def.inc'
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firmware.asm(74): Including file 'macros.asm'
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; Project name: memory-led-game
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; Description: Simple memory game using leds
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; Source code: https://github.com/sergeyyarkov/attiny24a_memory-led-game
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; Device: ATtiny24A
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; Package: 14-pin-PDIP_SOIC
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; Assembler: AVR macro assembler 2.2.7
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; Clock frequency: 8MHz with CKDIV8
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; Fuses: lfuse: 0x42, hfuse: 0xDF, efuse: 0xFF, lock:0xFF
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;
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; Written by Sergey Yarkov 27.09.2021
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.include "def.inc" ; Include type definitions of MCU
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;***** Created: 2011-02-09 12:04 ******* Source: ATtiny24A.xml ***********
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn24Adef.inc"
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;* Title : Register/Bit Definitions for the ATtiny24A
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;* Date : 2011-02-09
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;* Version : 2.35
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny24A
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN24ADEF_INC_
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#define _TN24ADEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny24A
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#pragma AVRPART ADMIN PART_NAME ATtiny24A
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x91
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.equ SIGNATURE_002 = 0x0b
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#pragma AVRPART CORE CORE_VERSION V2
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#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ OCR0B = 0x3c
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK0 = 0x39
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.equ TIFR0 = 0x38
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.equ SPMCSR = 0x37
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.equ OCR0A = 0x36
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0B = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ TCCR0A = 0x30
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.equ TCCR1A = 0x2f
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.equ TCCR1B = 0x2e
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.equ TCNT1L = 0x2c
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.equ TCNT1H = 0x2d
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.equ OCR1AL = 0x2a
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.equ OCR1AH = 0x2b
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.equ OCR1BL = 0x28
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.equ OCR1BH = 0x29
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.equ DWDR = 0x27
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.equ CLKPR = 0x26
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.equ ICR1L = 0x24
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.equ ICR1H = 0x25
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.equ GTCCR = 0x23
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.equ TCCR1C = 0x22
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.equ WDTCSR = 0x21
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.equ PCMSK1 = 0x20
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.equ EEARH = 0x1f
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.equ EEARL = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTA = 0x1b
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.equ DDRA = 0x1a
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.equ PINA = 0x19
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ GPIOR2 = 0x15
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.equ GPIOR1 = 0x14
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.equ GPIOR0 = 0x13
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.equ PCMSK0 = 0x12
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.equ USIBR = 0x10
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.equ USIDR = 0x0f
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.equ USISR = 0x0e
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.equ USICR = 0x0d
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.equ TIMSK1 = 0x0c
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.equ TIFR1 = 0x0b
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSRA = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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.equ ADCSRB = 0x03
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.equ DIDR0 = 0x01
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.equ PRR = 0x00
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; ***** BIT DEFINITIONS **************************************************
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; ***** PORTA ************************
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; PORTA - Port A Data Register
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.equ PORTA0 = 0 ; Port A Data Register bit 0
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.equ PA0 = 0 ; For compatibility
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.equ PORTA1 = 1 ; Port A Data Register bit 1
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.equ PA1 = 1 ; For compatibility
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.equ PORTA2 = 2 ; Port A Data Register bit 2
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.equ PA2 = 2 ; For compatibility
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.equ PORTA3 = 3 ; Port A Data Register bit 3
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.equ PA3 = 3 ; For compatibility
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.equ PORTA4 = 4 ; Port A Data Register bit 4
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.equ PA4 = 4 ; For compatibility
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.equ PORTA5 = 5 ; Port A Data Register bit 5
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.equ PA5 = 5 ; For compatibility
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.equ PORTA6 = 6 ; Port A Data Register bit 6
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.equ PA6 = 6 ; For compatibility
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.equ PORTA7 = 7 ; Port A Data Register bit 7
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.equ PA7 = 7 ; For compatibility
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; DDRA - Port A Data Direction Register
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.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
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.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
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.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
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.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
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.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
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.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
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.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
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.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
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; PINA - Port A Input Pins
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.equ PINA0 = 0 ; Input Pins, Port A bit 0
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.equ PINA1 = 1 ; Input Pins, Port A bit 1
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.equ PINA2 = 2 ; Input Pins, Port A bit 2
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.equ PINA3 = 3 ; Input Pins, Port A bit 3
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.equ PINA4 = 4 ; Input Pins, Port A bit 4
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.equ PINA5 = 5 ; Input Pins, Port A bit 5
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.equ PINA6 = 6 ; Input Pins, Port A bit 6
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.equ PINA7 = 7 ; Input Pins, Port A bit 7
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; ***** PORTB ************************
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; PORTB - Data Register, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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; PINB - Input Pins, Port B
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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; ***** ANALOG_COMPARATOR ************
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; ADCSRB - ADC Control and Status Register B
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.equ ACME = 6 ; Analog Comparator Multiplexer Enable
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIC = 2 ; Analog Comparator Input Capture Enable
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ AINBG = ACBG ; For compatibility
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.equ ACD = 7 ; Analog Comparator Disable
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; DIDR0 -
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.equ ADC0D = 0 ; ADC 0 Digital input buffer disable
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.equ ADC1D = 1 ; ADC 1 Digital input buffer disable
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; ***** AD_CONVERTER *****************
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; ADMUX - ADC Multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bit 0
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bit 1
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.equ MUX2 = 2 ; Analog Channel and Gain Selection Bit 2
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.equ MUX3 = 3 ; Analog Channel and Gain Selection Bit 3
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.equ MUX4 = 4 ; Analog Channel and Gain Selection Bit 4
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.equ MUX5 = 5 ; Analog Channel and Gain Selection Bit 5
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.equ REFS0 = 6 ; Reference Selection Bit 0
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.equ REFS1 = 7 ; Reference Selection Bit 1
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; ADCSRA - ADC Control and Status Register A
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.equ ADPS0 = 0 ; ADC Prescaler Select Bit 0
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.equ ADPS1 = 1 ; ADC Prescaler Select Bit 1
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.equ ADPS2 = 2 ; ADC Prescaler Select Bit 2
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADATE = 5 ; ADC Auto Trigger Enable
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
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.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
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.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
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.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
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.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
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.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
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.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
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; ADCL - ADC Data Register Low Byte
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.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
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; ADCSRB - ADC Control and Status Register B
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.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0
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.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1
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.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2
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.equ ADLAR = 4 ; ADC Left Adjust Result
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.equ BIN = 7 ; Bipolar Input Mode
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; DIDR0 - Digital Input Disable Register 0
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;.equ ADC0D = 0 ; ADC0 Digital Input Disable
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;.equ ADC1D = 1 ; ADC1 Digital Input Disable
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.equ ADC2D = 2 ; ADC2 Digital Input Disable
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.equ ADC3D = 3 ; ADC3 Digital Input Disable
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.equ ADC4D = 4 ; ADC4 Digital Input Disable
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.equ ADC5D = 5 ; ADC5 Digital Input Disable
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.equ ADC6D = 6 ; ADC6 Digital Input Disable
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.equ ADC7D = 7 ; ADC7 Digital Input Disable
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; ***** USI **************************
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; USIBR - USI Buffer Register
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.equ USIBR0 = 0 ; USI Buffer Register bit 0
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.equ USIBR1 = 1 ; USI Buffer Register bit 1
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.equ USIBR2 = 2 ; USI Buffer Register bit 2
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.equ USIBR3 = 3 ; USI Buffer Register bit 3
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.equ USIBR4 = 4 ; USI Buffer Register bit 4
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.equ USIBR5 = 5 ; USI Buffer Register bit 5
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.equ USIBR6 = 6 ; USI Buffer Register bit 6
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.equ USIBR7 = 7 ; USI Buffer Register bit 7
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; USIDR - USI Data Register
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.equ USIDR0 = 0 ; USI Data Register bit 0
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.equ USIDR1 = 1 ; USI Data Register bit 1
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.equ USIDR2 = 2 ; USI Data Register bit 2
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.equ USIDR3 = 3 ; USI Data Register bit 3
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.equ USIDR4 = 4 ; USI Data Register bit 4
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.equ USIDR5 = 5 ; USI Data Register bit 5
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.equ USIDR6 = 6 ; USI Data Register bit 6
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.equ USIDR7 = 7 ; USI Data Register bit 7
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; USISR - USI Status Register
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.equ USICNT0 = 0 ; USI Counter Value Bit 0
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.equ USICNT1 = 1 ; USI Counter Value Bit 1
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.equ USICNT2 = 2 ; USI Counter Value Bit 2
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.equ USICNT3 = 3 ; USI Counter Value Bit 3
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.equ USIDC = 4 ; Data Output Collision
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.equ USIPF = 5 ; Stop Condition Flag
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.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
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.equ USISIF = 7 ; Start Condition Interrupt Flag
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; USICR - USI Control Register
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.equ USITC = 0 ; Toggle Clock Port Pin
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.equ USICLK = 1 ; Clock Strobe
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.equ USICS0 = 2 ; USI Clock Source Select Bit 0
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.equ USICS1 = 3 ; USI Clock Source Select Bit 1
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.equ USIWM0 = 4 ; USI Wire Mode Bit 0
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.equ USIWM1 = 5 ; USI Wire Mode Bit 1
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.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
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.equ USISIE = 7 ; Start Condition Interrupt Enable
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; ***** EXTERNAL_INTERRUPT ***********
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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; GIMSK - General Interrupt Mask Register
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.equ GICR = GIMSK ; For compatibility
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.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0
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.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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; GIFR - General Interrupt Flag register
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.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0
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.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1
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.equ INTF0 = 6 ; External Interrupt Flag 0
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; PCMSK1 - Pin Change Enable Mask 1
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.equ PCINT8 = 0 ; Pin Change Enable Mask Bit 8
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.equ PCINT9 = 1 ; Pin Change Enable Mask Bit 9
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.equ PCINT10 = 2 ; Pin Change Enable Mask Bit 10
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.equ PCINT11 = 3 ; Pin Change Enable Mask Bit 11
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; PCMSK0 - Pin Change Enable Mask 0
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.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0
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.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1
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.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2
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.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3
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.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4
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.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5
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.equ PCINT6 = 6 ; Pin Change Enable Mask Bit 6
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.equ PCINT7 = 7 ; Pin Change Enable Mask Bit 7
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; ***** EEPROM ***********************
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; EEARL - EEPROM Address Register Low Byte
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.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
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.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
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.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
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; EEARH - EEPROM Address Register High Byte
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.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEPE = 1 ; EEPROM Write Enable
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.equ EEMPE = 2 ; EEPROM Master Write Enable
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.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
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.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
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.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
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; ***** WATCHDOG *********************
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; WDTCSR - Watchdog Timer Control Register
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.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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.equ WDE = 3 ; Watch Dog Enable
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.equ WDCE = 4 ; Watchdog Change Enable
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.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
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.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
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.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
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; ***** TIMER_COUNTER_0 **************
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; TIMSK0 - Timer/Counter Interrupt Mask Register
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.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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; TIFR0 - Timer/Counter0 Interrupt Flag Register
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.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag A
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.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag B
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; TCCR0A - Timer/Counter Control Register A
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.equ WGM00 = 0 ; Waveform Generation Mode bit 0
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.equ WGM01 = 1 ; Waveform Generation Mode bit 1
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.equ COM0B0 = 4 ; Compare Match Output B Mode bit 0
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.equ COM0B1 = 5 ; Compare Match Output B Mode bit 1
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.equ COM0A0 = 6 ; Compare Match Output A Mode bit 0
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.equ COM0A1 = 7 ; Compare Match Output A Mode bit 1
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; TCCR0B - Timer/Counter Control Register B
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.equ CS00 = 0 ; Clock Select bit 0
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.equ CS01 = 1 ; Clock Select bit 1
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.equ CS02 = 2 ; Clock Select bit 2
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.equ WGM02 = 3 ; Waveform Generation Mode bit 2
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.equ FOC0B = 6 ; Force Output Compare B
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.equ FOC0A = 7 ; Force Output Compare A
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; TCNT0 - Timer/Counter0
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.equ TCNT0_0 = 0 ;
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|
.equ TCNT0_1 = 1 ;
|
|
.equ TCNT0_2 = 2 ;
|
|
.equ TCNT0_3 = 3 ;
|
|
.equ TCNT0_4 = 4 ;
|
|
.equ TCNT0_5 = 5 ;
|
|
.equ TCNT0_6 = 6 ;
|
|
.equ TCNT0_7 = 7 ;
|
|
|
|
; OCR0A - Timer/Counter0 Output Compare Register A
|
|
.equ OCR0A_0 = 0 ;
|
|
.equ OCR0A_1 = 1 ;
|
|
.equ OCR0A_2 = 2 ;
|
|
.equ OCR0A_3 = 3 ;
|
|
.equ OCR0A_4 = 4 ;
|
|
.equ OCR0A_5 = 5 ;
|
|
.equ OCR0A_6 = 6 ;
|
|
.equ OCR0A_7 = 7 ;
|
|
|
|
; OCR0B - Timer/Counter0 Output Compare Register B
|
|
.equ OCR0_0 = 0 ;
|
|
.equ OCR0_1 = 1 ;
|
|
.equ OCR0_2 = 2 ;
|
|
.equ OCR0_3 = 3 ;
|
|
.equ OCR0_4 = 4 ;
|
|
.equ OCR0_5 = 5 ;
|
|
.equ OCR0_6 = 6 ;
|
|
.equ OCR0_7 = 7 ;
|
|
|
|
; GTCCR - General Timer/Counter Control Register
|
|
.equ PSR10 = 0 ; Prescaler Reset Timer/CounterN
|
|
.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
|
|
|
|
|
; ***** TIMER_COUNTER_1 **************
|
|
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
|
|
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
|
|
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable
|
|
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable
|
|
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
|
|
|
|
; TIFR1 - Timer/Counter Interrupt Flag register
|
|
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
|
|
.equ OCF1A = 1 ; Timer/Counter1 Output Compare A Match Flag
|
|
.equ OCF1B = 2 ; Timer/Counter1 Output Compare B Match Flag
|
|
.equ ICF1 = 5 ; Timer/Counter1 Input Capture Flag
|
|
|
|
; TCCR1A - Timer/Counter1 Control Register A
|
|
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0
|
|
.equ PWM10 = WGM10 ; For compatibility
|
|
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1
|
|
.equ PWM11 = WGM11 ; For compatibility
|
|
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0
|
|
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
|
|
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
|
|
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
|
|
|
|
; TCCR1B - Timer/Counter1 Control Register B
|
|
.equ CS10 = 0 ; Clock Select bit 0
|
|
.equ CS11 = 1 ; Clock Select 1 bit 1
|
|
.equ CS12 = 2 ; Clock Select1 bit 2
|
|
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2
|
|
.equ CTC1 = WGM12 ; For compatibility
|
|
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3
|
|
.equ ICES1 = 6 ; Input Capture 1 Edge Select
|
|
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
|
|
|
|
; TCCR1C - Timer/Counter1 Control Register C
|
|
.equ FOC1B = 6 ; Force Output Compare for Channel B
|
|
.equ FOC1A = 7 ; Force Output Compare for Channel A
|
|
|
|
|
|
; ***** CPU **************************
|
|
; SREG - Status Register
|
|
.equ SREG_C = 0 ; Carry Flag
|
|
.equ SREG_Z = 1 ; Zero Flag
|
|
.equ SREG_N = 2 ; Negative Flag
|
|
.equ SREG_V = 3 ; Two's Complement Overflow Flag
|
|
.equ SREG_S = 4 ; Sign Bit
|
|
.equ SREG_H = 5 ; Half Carry Flag
|
|
.equ SREG_T = 6 ; Bit Copy Storage
|
|
.equ SREG_I = 7 ; Global Interrupt Enable
|
|
|
|
; SPL - Stack Pointer Low
|
|
.equ SP0 = 0 ; Stack pointer bit 0
|
|
.equ SP1 = 1 ; Stack pointer bit 1
|
|
.equ SP2 = 2 ; Stack pointer bit 2
|
|
.equ SP3 = 3 ; Stack pointer bit 3
|
|
.equ SP4 = 4 ; Stack pointer bit 4
|
|
.equ SP5 = 5 ; Stack pointer bit 5
|
|
.equ SP6 = 6 ; Stack pointer bit 6
|
|
.equ SP7 = 7 ; Stack pointer bit 7
|
|
|
|
; MCUCR - MCU Control Register
|
|
.equ BODSE = 2 ; BOD Sleep Enable
|
|
.equ SM0 = 3 ; Sleep Mode Select Bit 0
|
|
.equ SM1 = 4 ; Sleep Mode Select Bit 1
|
|
.equ SE = 5 ; Sleep Enable
|
|
.equ PUD = 6 ;
|
|
.equ BODS = 7 ; BOD Sleep
|
|
|
|
; MCUSR - MCU Status Register
|
|
.equ PORF = 0 ; Power-on reset flag
|
|
.equ EXTRF = 1 ; External Reset Flag
|
|
.equ BORF = 2 ; Brown-out Reset Flag
|
|
.equ WDRF = 3 ; Watchdog Reset Flag
|
|
|
|
; OSCCAL - Oscillator Calibration Value
|
|
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
|
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
|
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
|
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
|
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
|
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
|
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
|
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
|
|
|
; GPIOR2 - General Purpose I/O Register 2
|
|
.equ GPIOR20 = 0 ;
|
|
.equ GPIOR21 = 1 ;
|
|
.equ GPIOR22 = 2 ;
|
|
.equ GPIOR23 = 3 ;
|
|
.equ GPIOR24 = 4 ;
|
|
.equ GPIOR25 = 5 ;
|
|
.equ GPIOR26 = 6 ;
|
|
.equ GPIOR27 = 7 ;
|
|
|
|
; GPIOR1 - General Purpose I/O Register 1
|
|
.equ GPIOR10 = 0 ;
|
|
.equ GPIOR11 = 1 ;
|
|
.equ GPIOR12 = 2 ;
|
|
.equ GPIOR13 = 3 ;
|
|
.equ GPIOR14 = 4 ;
|
|
.equ GPIOR15 = 5 ;
|
|
.equ GPIOR16 = 6 ;
|
|
.equ GPIOR17 = 7 ;
|
|
|
|
; GPIOR0 - General Purpose I/O Register 0
|
|
.equ GPIOR00 = 0 ;
|
|
.equ GPIOR01 = 1 ;
|
|
.equ GPIOR02 = 2 ;
|
|
.equ GPIOR03 = 3 ;
|
|
.equ GPIOR04 = 4 ;
|
|
.equ GPIOR05 = 5 ;
|
|
.equ GPIOR06 = 6 ;
|
|
.equ GPIOR07 = 7 ;
|
|
|
|
; PRR - Power Reduction Register
|
|
.equ PRADC = 0 ; Power Reduction ADC
|
|
.equ PRUSI = 1 ; Power Reduction USI
|
|
.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0
|
|
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
|
|
|
|
; CLKPR - Clock Prescale Register
|
|
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
|
|
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
|
|
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
|
|
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
|
|
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
|
|
|
|
|
|
; ***** BOOT_LOAD ********************
|
|
; SPMCSR - Store Program Memory Control Register
|
|
.equ SPMEN = 0 ; Store Program Memory Enable
|
|
.equ PGERS = 1 ; Page Erase
|
|
.equ PGWRT = 2 ; Page Write
|
|
.equ RFLB = 3 ; Read fuse and lock bits
|
|
.equ CTPB = 4 ; Clear temporary page buffer
|
|
|
|
|
|
|
|
; ***** LOCKSBITS ********************************************************
|
|
.equ LB1 = 0 ; Lockbit
|
|
.equ LB2 = 1 ; Lockbit
|
|
|
|
|
|
; ***** FUSES ************************************************************
|
|
; LOW fuse bits
|
|
.equ CKSEL0 = 0 ; Select Clock source
|
|
.equ CKSEL1 = 1 ; Select Clock source
|
|
.equ CKSEL2 = 2 ; Select Clock source
|
|
.equ CKSEL3 = 3 ; Select Clock source
|
|
.equ SUT0 = 4 ; Select start-up time
|
|
.equ SUT1 = 5 ; Select start-up time
|
|
.equ CKOUT = 6 ; Clock Output Enable
|
|
.equ CKDIV8 = 7 ; Divide clock by 8
|
|
|
|
; HIGH fuse bits
|
|
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
|
|
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
|
|
.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase
|
|
.equ WDTON = 4 ; Watchdog Timer always on
|
|
.equ SPIEN = 5 ; Enable Serial Program and Data Downloading
|
|
.equ DWEN = 6 ; DebugWIRE Enable
|
|
.equ RSTDISBL = 7 ; External Reset disable
|
|
|
|
; EXTENDED fuse bits
|
|
.equ SELFPRGEN = 0 ; Self-Programming Enable
|
|
|
|
|
|
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
|
.def XH = r27
|
|
.def XL = r26
|
|
.def YH = r29
|
|
.def YL = r28
|
|
.def ZH = r31
|
|
.def ZL = r30
|
|
|
|
|
|
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
|
.equ FLASHEND = 0x03ff ; Note: Word address
|
|
.equ IOEND = 0x003f
|
|
.equ SRAM_START = 0x0060
|
|
.equ SRAM_SIZE = 128
|
|
.equ RAMEND = 0x00df
|
|
.equ XRAMEND = 0x0000
|
|
.equ E2END = 0x007f
|
|
.equ EEPROMEND = 0x007f
|
|
.equ EEADRBITS = 7
|
|
#pragma AVRPART MEMORY PROG_FLASH 2048
|
|
#pragma AVRPART MEMORY EEPROM 128
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 128
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
|
|
|
|
|
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
|
.equ NRWW_START_ADDR = 0x0
|
|
.equ NRWW_STOP_ADDR = 0x3ff
|
|
.equ RWW_START_ADDR = 0x0
|
|
.equ RWW_STOP_ADDR = 0x0
|
|
.equ PAGESIZE = 16
|
|
|
|
|
|
|
|
; ***** INTERRUPT VECTORS ************************************************
|
|
.equ EXT_INT0addr = 0x0001 ; External Interrupt Request 0
|
|
.equ PCI0addr = 0x0002 ; Pin Change Interrupt Request 0
|
|
.equ PCI1addr = 0x0003 ; Pin Change Interrupt Request 1
|
|
.equ WATCHDOGaddr = 0x0004 ; Watchdog Time-out
|
|
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event
|
|
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
|
|
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
|
|
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
|
|
.equ OC0Aaddr = 0x0009 ; Timer/Counter0 Compare Match A
|
|
.equ OC0Baddr = 0x000a ; Timer/Counter0 Compare Match B
|
|
.equ OVF0addr = 0x000b ; Timer/Counter0 Overflow
|
|
.equ ACIaddr = 0x000c ; Analog Comparator
|
|
.equ ADCCaddr = 0x000d ; ADC Conversion Complete
|
|
.equ ERDYaddr = 0x000e ; EEPROM Ready
|
|
.equ USI_STRaddr = 0x000f ; USI START
|
|
.equ USI_OVFaddr = 0x0010 ; USI Overflow
|
|
|
|
.equ INT_VECTORS_SIZE = 17 ; size in words
|
|
|
|
#endif /* _TN24ADEF_INC_ */
|
|
|
|
; ***** END OF FILE ******************************************************
|
|
.list ; Enable listing
|
|
|
|
;
|
|
; Registers
|
|
.def seq_length_r = r10 ; Current length of sequence
|
|
.def wdt_counter = r11 ; Counter for wathdog timer
|
|
.def temp_r = r16 ; Temp general register A
|
|
.def temp_r_b = r23 ; Temp general register B
|
|
.def temp_r_c = r26 ; Temp general register C
|
|
.def mcu_state_r = r17 ; Current state of MCU. This register will be compared in an main loop
|
|
.def delay_counter_r = r19 ; Register for storing delay counter
|
|
.def poll_step_r = r20 ; Current poll step for checking the input with answer
|
|
|
|
;
|
|
; LEDS constants
|
|
.equ LED_DIR = DDRA
|
|
.equ LED_PORT = PORTA
|
|
.equ LED_PIN = PINA
|
|
.equ LED_PIN_0 = PINA0
|
|
.equ LED_PIN_1 = PINA1
|
|
.equ LED_PIN_2 = PINA2
|
|
.equ LED_PIN_3 = PINA3
|
|
|
|
;
|
|
; Buttons constants
|
|
.equ SW_DIR = DDRA
|
|
.equ SW_PORT = PORTA
|
|
.equ SW_PIN = PINA
|
|
.equ SW_PIN_4 = PINA4
|
|
.equ SW_PIN_5 = PINA5
|
|
.equ SW_PIN_6 = PINA6
|
|
.equ SW_PIN_7 = PINA7
|
|
|
|
;
|
|
; Buzzer constants
|
|
.equ BUZZ_DIR = DDRB
|
|
.equ BUZZ_PORT = PORTB
|
|
.equ BUZZ_PIN = PINB2
|
|
|
|
;
|
|
; States constants
|
|
.equ INIT_STATE = 0x01
|
|
.equ SHOWING_STATE = 0x02
|
|
.equ POLLING_STATE = 0x03
|
|
|
|
;
|
|
; SW Flags states constants
|
|
.equ SW_FLAG_1 = 0xe0
|
|
.equ SW_FLAG_2 = 0xd0
|
|
.equ SW_FLAG_3 = 0xb0
|
|
.equ SW_FLAG_4 = 0x70
|
|
|
|
.equ SEQ_LENGTH = 2
|
|
|
|
; Value that stored in OCR0A for each tone
|
|
; 880Hz = 71
|
|
; 785Hz = 80
|
|
; 590Hz = 105
|
|
; 440Hz = 142
|
|
|
|
.include "macros.asm" ; Include macros
|
|
|
|
; Initialize stack pointer
|
|
; @0 - Temp register
|
|
.macro init_stack_p
|
|
ldi @0, low(@1)
|
|
out SPL, @0
|
|
clr @0
|
|
.ifdef SPH
|
|
ldi @0, high(RAMEND)
|
|
out SPH, @0
|
|
clr @0
|
|
.endif
|
|
.endm
|
|
|
|
;
|
|
; out immediate
|
|
; @0 - I/O Register
|
|
; @1 - Data to write
|
|
.macro outi
|
|
push temp_r
|
|
ldi temp_r, @1
|
|
out @0, temp_r
|
|
pop temp_r
|
|
.endm
|
|
|
|
;
|
|
; sts immediate
|
|
; @0 - SRAM Address
|
|
; @1 - Data to write
|
|
.macro stsi
|
|
push temp_r
|
|
ldi temp_r, @1
|
|
sts @0, temp_r
|
|
pop temp_r
|
|
.endm
|
|
|
|
;
|
|
; Set MCU global state
|
|
; @0 - New state
|
|
.macro set_state
|
|
sts PREVIOUS_STATE_ADDRESS, mcu_state_r ; Write previous state to SRAM
|
|
stsi CURRENT_STATE_ADDRESS, @0
|
|
.endm
|
|
|
|
.macro buzzer_on
|
|
sbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
.macro buzzer_off
|
|
cbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
.macro beep_led_1
|
|
outi OCR0A, 142
|
|
sbi LED_PORT, 0
|
|
sbi BUZZ_DIR, BUZZ_PIN
|
|
rcall delay
|
|
cbi LED_PORT, 0
|
|
cbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
.macro beep_led_2
|
|
outi OCR0A, 71
|
|
sbi LED_PORT, 1
|
|
sbi BUZZ_DIR, BUZZ_PIN
|
|
rcall delay
|
|
cbi LED_PORT, 1
|
|
cbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
.macro beep_led_3
|
|
outi OCR0A, 105
|
|
sbi LED_PORT, 2
|
|
sbi BUZZ_DIR, BUZZ_PIN
|
|
rcall delay
|
|
cbi LED_PORT, 2
|
|
cbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
.macro beep_led_4
|
|
outi OCR0A, 80
|
|
sbi LED_PORT, 3
|
|
sbi BUZZ_DIR, BUZZ_PIN
|
|
rcall delay
|
|
cbi LED_PORT, 3
|
|
cbi BUZZ_DIR, BUZZ_PIN
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.dseg ; Data segment
|
|
.org SRAM_START
|
|
|
|
; MCU Global states addresses
|
|
000060 CURRENT_STATE_ADDRESS: .byte 0x01
|
|
000061 PREVIOUS_STATE_ADDRESS: .byte 0x01
|
|
|
|
; Button flags
|
|
000062 SW_FLAGS_ADDRESS: .byte 0x01
|
|
|
|
.cseg ; Code segment
|
|
.org 0x00
|
|
|
|
; MCU vectors
|
|
000000 c054 rjmp RESET_vect ; Program start at RESET vector
|
|
000001 9518 reti ; External Interrupt Request 0 / inactive
|
|
000002 c013 rjmp PCINT0_vect ; Pin Change Interrupt Request 0 / active
|
|
000003 9518 reti ; Pin Change Interrupt Request 1 / inactive
|
|
000004 c00c rjmp WDT_vect ; Watchdog Time-out / active
|
|
000005 9518 reti ; Timer/Counter1 Capture Event / inactive
|
|
000006 9518 reti ; Timer/Counter1 Compare Match A / inactive
|
|
000007 9518 reti ; Timer/Counter1 Compare Match B / inactive
|
|
000008 9518 reti ; Timer/Counter1 Overflow / inactive
|
|
000009 9518 reti ; Timer/Counter0 Compare Match A / inactive
|
|
00000a 9518 reti ; Timer/Counter0 Compare Match B / inactive
|
|
00000b c01e rjmp TIM0_OVF_vect ; Timer/Counter0 Overflow / active
|
|
00000c 9518 reti ; Analog Comparator / inactive
|
|
00000d 9518 reti ; ADC Conversion Complete / inactive
|
|
00000e 9518 reti ; EEPROM Ready / inactive
|
|
00000f 9518 reti ; USI START / inactive
|
|
000010 9518 reti ; USI Overflow / inactive
|
|
|
|
; watchdog time-out interrupt handler
|
|
WDT_vect:
|
|
000011 94b3 inc wdt_counter
|
|
000012 b5a1 in temp_r_c, WDTCSR
|
|
000013 64a0 ori temp_r_c, (1<<WDIE)
|
|
000014 bda1 out WDTCSR, temp_r_c
|
|
000015 9518 reti
|
|
|
|
; pin change on button interrupt handler
|
|
PCINT0_vect:
|
|
000016 931f push r17
|
|
000017 932f push r18
|
|
000018 24bb clr wdt_counter
|
|
000019 b725 in r18, MCUCR
|
|
00001a 7d2f cbr r18, (1<<SE)
|
|
; turn off the sleep mode
|
|
00001b bf25 out MCUCR, r18
|
|
; save status register
|
|
00001c b72f in r18, SREG
|
|
00001d 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS
|
|
00001f 3013 cpi mcu_state_r, POLLING_STATE
|
|
; do not change button flags unless in POLLING state of mcu
|
|
000020 f431 brne quit
|
|
000021 b319 in r17, PINA
|
|
; get pins status of only buttons
|
|
000022 7f10 andi r17, 0xf0
|
|
; button debounce
|
|
000023 d1b8 rcall delay_20ms
|
|
; update flag status in SRAM
|
|
000024 9310 0062 sts SW_FLAGS_ADDRESS, r17
|
|
000026 bf2f out SREG, r18
|
|
|
|
quit:
|
|
000027 912f pop r18
|
|
000028 911f pop r17
|
|
000029 9518 reti
|
|
|
|
; random byte generator
|
|
TIM0_OVF_vect:
|
|
00002a 937f push temp_r_b
|
|
00002b b77f in temp_r_b, SREG
|
|
|
|
00002c c002 rjmp gen_start
|
|
|
|
00002d ea08 ldi temp_r, 168
|
|
00002e b752 in r21, TCNT0
|
|
|
|
gen_start:
|
|
00002f 2705 eor temp_r, r21
|
|
000030 9502 swap temp_r
|
|
000031 0f50 add r21, temp_r
|
|
000032 bf7f out SREG, temp_r_b
|
|
000033 917f pop temp_r_b
|
|
000034 9518 reti
|
|
|
|
; initialize MCU
|
|
MCU_Init:
|
|
000035 d184 rcall init_ports
|
|
000036 d173 rcall init_interrupts
|
|
000037 d178 rcall init_buzzer
|
|
000038 d18c rcall init_wdt
|
|
000039 d187 rcall init_sm
|
|
|
|
; init important registers for game
|
|
00003a ef3f ldi delay_counter_r, 0xff
|
|
00003b e041 ldi poll_step_r, 1
|
|
00003c e0a2 ldi temp_r_c, SEQ_LENGTH
|
|
00003d 2eaa mov seq_length_r, temp_r_c
|
|
00003e 27ff clr ZH
|
|
00003f e8e0 ldi ZL, $80
|
|
|
|
; delay before start main loop
|
|
000040 d002 rcall MCU_Delay
|
|
|
|
000041 9478 sei
|
|
000042 9508 ret
|
|
|
|
MCU_Delay:
|
|
000043 e073 ldi temp_r_b, 3
|
|
_init_loop_loading:
|
|
000044 d113 rcall effect_1
|
|
000045 957a dec temp_r_b
|
|
000046 f7e9 brne _init_loop_loading
|
|
000047 d1ab rcall delay_1s
|
|
000048 2777 clr temp_r_b
|
|
000049 9508 ret
|
|
|
|
WDT_off:
|
|
00004a 94f8 cli
|
|
00004b 95a8 wdr
|
|
; clear WDRF in MCUSR
|
|
00004c e000 ldi temp_r, (0<<WDRF)
|
|
00004d bf04 out MCUSR, r16
|
|
; write logical one to WDCE and WDE
|
|
; keep old prescaler setting to prevent unintentional Watchdog Reset
|
|
00004e b501 in temp_r, WDTCSR
|
|
00004f 6108 ori temp_r, (1<<WDCE)|(1<<WDE)
|
|
000050 bd01 out WDTCSR, temp_r
|
|
; turn off WDT
|
|
000051 e000 ldi temp_r, (0<<WDE)
|
|
000052 bd01 out WDTCSR, temp_r
|
|
000053 9478 sei
|
|
000054 9508 ret
|
|
|
|
; program start at reset vector
|
|
RESET_vect:
|
|
000055 ed0f
|
|
000056 bf0d
|
|
000057 2700 init_stack_p temp_r, RAMEND
|
|
000058 9310 0061
|
|
00005a 930f
|
|
00005b e001
|
|
00005c 9300 0060
|
|
00005e 910f set_state INIT_STATE
|
|
|
|
; main program loop
|
|
loop:
|
|
00005f e1a4 ldi temp_r_c, 20
|
|
000060 16ba cp wdt_counter, temp_r_c
|
|
000061 f408 brsh _mcu_sleep
|
|
000062 c007 rjmp feed
|
|
_mcu_sleep:
|
|
000063 24bb clr wdt_counter
|
|
000064 dfe5 rcall WDT_off
|
|
000065 b7a5 in temp_r_c, MCUCR
|
|
000066 62a0 sbr temp_r_c, (1<<SE)
|
|
000067 bfa5 out MCUCR, temp_r_c
|
|
000068 94f8 cli
|
|
000069 9588 sleep
|
|
feed:
|
|
00006a 9110 0060 lds mcu_state_r, CURRENT_STATE_ADDRESS
|
|
; init state
|
|
init:
|
|
00006c 3011 cpi mcu_state_r, INIT_STATE
|
|
00006d f441 brne showing
|
|
00006e dfc6 rcall MCU_Init
|
|
00006f 9310 0061
|
|
000071 930f
|
|
000072 e002
|
|
000073 9300 0060
|
|
000075 910f set_state SHOWING_STATE
|
|
|
|
; showing state
|
|
showing:
|
|
000076 3012 cpi mcu_state_r, SHOWING_STATE
|
|
000077 f441 brne polling
|
|
; generate sequence and save answer to SRAM
|
|
000078 d093 rcall show_sequence
|
|
000079 9310 0061
|
|
00007b 930f
|
|
00007c e003
|
|
00007d 9300 0060
|
|
00007f 910f set_state POLLING_STATE
|
|
|
|
; polling state
|
|
polling:
|
|
000080 3013 cpi mcu_state_r, POLLING_STATE
|
|
000081 f5c1 brne default
|
|
btn_1:
|
|
000082 9120 0062 lds r18, SW_FLAGS_ADDRESS
|
|
000084 3e20 cpi r18, SW_FLAG_1
|
|
000085 f451 brne btn_2
|
|
led_on_1:
|
|
000086 930f
|
|
000087 e80e
|
|
000088 bf06
|
|
000089 910f outi OCR0A, 142
|
|
00008a 9ad8 sbi LED_PORT, 0
|
|
00008b 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
00008c d02f rcall btn_handler
|
|
00008d 98d8 cbi LED_PORT, 0
|
|
00008e 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
00008f cff2 rjmp btn_1
|
|
|
|
btn_2:
|
|
000090 9120 0062 lds r18, SW_FLAGS_ADDRESS
|
|
000092 3d20 cpi r18, SW_FLAG_2
|
|
000093 f451 brne btn_3
|
|
led_on_2:
|
|
000094 930f
|
|
000095 e407
|
|
000096 bf06
|
|
000097 910f outi OCR0A, 71
|
|
000098 9ad9 sbi LED_PORT, 1
|
|
000099 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
00009a d021 rcall btn_handler
|
|
00009b 98d9 cbi LED_PORT, 1
|
|
00009c 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
00009d cff2 rjmp btn_2
|
|
|
|
btn_3:
|
|
00009e 9120 0062 lds r18, SW_FLAGS_ADDRESS
|
|
0000a0 3b20 cpi r18, SW_FLAG_3
|
|
0000a1 f451 brne btn_4
|
|
led_on_3:
|
|
0000a2 930f
|
|
0000a3 e609
|
|
0000a4 bf06
|
|
0000a5 910f outi OCR0A, 105
|
|
0000a6 9ada sbi LED_PORT, 2
|
|
0000a7 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
0000a8 d013 rcall btn_handler
|
|
0000a9 98da cbi LED_PORT, 2
|
|
0000aa 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
0000ab cff2 rjmp btn_3
|
|
|
|
btn_4:
|
|
0000ac 9120 0062 lds r18, SW_FLAGS_ADDRESS
|
|
0000ae 3720 cpi r18, SW_FLAG_4
|
|
0000af f451 brne default
|
|
led_on_4:
|
|
0000b0 930f
|
|
0000b1 e500
|
|
0000b2 bf06
|
|
0000b3 910f outi OCR0A, 80
|
|
0000b4 9adb sbi LED_PORT, 3
|
|
0000b5 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
0000b6 d005 rcall btn_handler
|
|
0000b7 98db cbi LED_PORT, 3
|
|
0000b8 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
0000b9 cff2 rjmp btn_4
|
|
|
|
default:
|
|
0000ba d092 rcall OCR0A_reset
|
|
0000bb cfa3 rjmp loop
|
|
|
|
; check the input value with answer in SRAM
|
|
btn_handler:
|
|
0000bc 932f push r18
|
|
0000bd d129 rcall delay_50ms
|
|
0000be d128 rcall delay_50ms
|
|
0000bf d127 rcall delay_50ms
|
|
0000c0 b3a9 in temp_r_c, PINA
|
|
0000c1 2f9a mov r25, temp_r_c
|
|
0000c2 7fa0 andi temp_r_c, 0xf0
|
|
0000c3 709f andi r25, 0x0f
|
|
0000c4 27aa clr temp_r_c
|
|
0000c5 93a0 0062 sts SW_FLAGS_ADDRESS, temp_r_c
|
|
|
|
0000c7 9181 ld r24, Z+
|
|
; check answer
|
|
0000c8 1798 cp r25, r24
|
|
; game over
|
|
0000c9 f429 brne _game_over
|
|
|
|
0000ca 2d2a mov r18, seq_length_r
|
|
0000cb 1724 cp r18, poll_step_r
|
|
0000cc f051 breq _btn_handler_exit_state
|
|
|
|
0000cd 9543 inc poll_step_r
|
|
|
|
0000ce c010 rjmp _btn_handler_exit
|
|
|
|
_game_over:
|
|
0000cf 912f pop r18
|
|
0000d0 d087 rcall effect_1
|
|
0000d1 ef3f ldi delay_counter_r, 0xff
|
|
0000d2 e0a2 ldi temp_r_c, SEQ_LENGTH
|
|
0000d3 95aa dec temp_r_c
|
|
0000d4 2eaa mov seq_length_r, temp_r_c
|
|
0000d5 d00c rcall reset_game
|
|
0000d6 9508 ret
|
|
|
|
_btn_handler_exit_state:
|
|
0000d7 912f pop r18
|
|
0000d8 ef00 ldi temp_r, 0xf0
|
|
0000d9 bb0b out LED_PORT, temp_r
|
|
0000da 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
0000db d10b rcall delay_50ms
|
|
0000dc d0a4 rcall effect_2
|
|
0000dd d004 rcall reset_game
|
|
0000de 9508 ret
|
|
|
|
_btn_handler_exit:
|
|
0000df 912f pop r18
|
|
0000e0 9508 ret
|
|
0000e1 9508 ret
|
|
|
|
reset_game:
|
|
0000e2 27ff clr ZH
|
|
0000e3 e8e0 ldi ZL, $80
|
|
0000e4 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
0000e5 ef00 ldi temp_r, 0xf0
|
|
0000e6 bb0b out LED_PORT, temp_r
|
|
0000e7 d10b rcall delay_1s
|
|
0000e8 9310 0061
|
|
0000ea 930f
|
|
0000eb e002
|
|
0000ec 9300 0060
|
|
0000ee 910f set_state SHOWING_STATE
|
|
0000ef e041 ldi poll_step_r, 1
|
|
0000f0 94a3 inc seq_length_r
|
|
0000f1 9508 ret
|
|
|
|
; generate random sequence of bytes for leds and save answer to SRAM
|
|
gen_ran_seq:
|
|
0000f2 2d7a mov temp_r_b, seq_length_r
|
|
0000f3 27dd clr YH
|
|
0000f4 e8c0 ldi YL, $80
|
|
|
|
_gen_ran_loop:
|
|
; delay is required
|
|
0000f5 d0f1 rcall delay_50ms
|
|
0000f6 2f65 mov r22, r21
|
|
0000f7 3466 cpi r22, 70
|
|
0000f8 f030 brlo _gen_answ_1
|
|
0000f9 386c cpi r22, 140
|
|
0000fa f030 brlo _gen_answ_2
|
|
0000fb 3c68 cpi r22, 200
|
|
0000fc f030 brlo _gen_answ_3
|
|
0000fd 3f6f cpi r22, 255
|
|
0000fe f030 brlo _gen_answ_4
|
|
|
|
_gen_answ_1:
|
|
0000ff e0a1 ldi temp_r_c, 0x01
|
|
000100 c005 rjmp _gen_ran_write
|
|
|
|
_gen_answ_2:
|
|
000101 e0a2 ldi temp_r_c, 0x02
|
|
000102 c003 rjmp _gen_ran_write
|
|
|
|
_gen_answ_3:
|
|
000103 e0a4 ldi temp_r_c, 0x04
|
|
000104 c001 rjmp _gen_ran_write
|
|
|
|
_gen_answ_4:
|
|
000105 e0a8 ldi temp_r_c, 0x08
|
|
|
|
_gen_ran_write:
|
|
000106 93a9 st Y+, temp_r_c
|
|
000107 957a dec temp_r_b
|
|
000108 3070 cpi temp_r_b, 0
|
|
000109 f759 brne _gen_ran_loop
|
|
00010a 0000 nop
|
|
00010b 9508 ret
|
|
|
|
show_sequence:
|
|
; answer stored in SRAM in addr $80:{SEQ_LENGTH}
|
|
00010c dfe5 rcall gen_ran_seq
|
|
show_start:
|
|
00010d 2d7a mov temp_r_b, seq_length_r
|
|
|
|
00010e 27dd clr YH
|
|
00010f e8c0 ldi YL, $80
|
|
|
|
_sequence_loop:
|
|
000110 3070 cpi temp_r_b, 0
|
|
000111 f1c1 breq _seq_quit
|
|
000112 91a9 ld temp_r_c, Y+
|
|
000113 30a1 cpi temp_r_c, 0x01
|
|
000114 f031 breq beep_1
|
|
000115 30a2 cpi temp_r_c, 0x02
|
|
000116 f079 breq beep_2
|
|
000117 30a4 cpi temp_r_c, 0x04
|
|
000118 f0c1 breq beep_3
|
|
000119 30a8 cpi temp_r_c, 0x08
|
|
00011a f109 breq beep_4
|
|
|
|
beep_1:
|
|
00011b 930f
|
|
00011c e80e
|
|
00011d bf06
|
|
00011e 910f
|
|
00011f 9ad8
|
|
000120 9aba
|
|
000121 d0ac
|
|
000122 98d8
|
|
000123 98ba beep_led_1
|
|
000124 d028 rcall OCR0A_reset
|
|
000125 c020 rjmp beep_quit
|
|
|
|
beep_2:
|
|
000126 930f
|
|
000127 e407
|
|
000128 bf06
|
|
000129 910f
|
|
00012a 9ad9
|
|
00012b 9aba
|
|
00012c d0a1
|
|
00012d 98d9
|
|
00012e 98ba beep_led_2
|
|
00012f d01d rcall OCR0A_reset
|
|
000130 c015 rjmp beep_quit
|
|
|
|
beep_3:
|
|
000131 930f
|
|
000132 e609
|
|
000133 bf06
|
|
000134 910f
|
|
000135 9ada
|
|
000136 9aba
|
|
000137 d096
|
|
000138 98da
|
|
000139 98ba beep_led_3
|
|
00013a d012 rcall OCR0A_reset
|
|
00013b c00a rjmp beep_quit
|
|
|
|
beep_4:
|
|
00013c 930f
|
|
00013d e500
|
|
00013e bf06
|
|
00013f 910f
|
|
000140 9adb
|
|
000141 9aba
|
|
000142 d08b
|
|
000143 98db
|
|
000144 98ba beep_led_4
|
|
000145 d007 rcall OCR0A_reset
|
|
|
|
beep_quit:
|
|
000146 d087 rcall delay
|
|
000147 957a dec temp_r_b
|
|
000148 3070 cpi temp_r_b, 0
|
|
000149 f631 brne _sequence_loop
|
|
|
|
_seq_quit:
|
|
00014a d007 rcall dec_delay_counter
|
|
00014b d09b rcall delay_50ms
|
|
00014c 9508 ret
|
|
|
|
; this function need to set the OCR0A register to 0xff for overflow interrupt
|
|
OCR0A_reset:
|
|
00014d 937f push temp_r_b
|
|
00014e ef7f ldi temp_r_b, 0xff
|
|
00014f bf76 out OCR0A, temp_r_b
|
|
000150 917f pop temp_r_b
|
|
000151 9508 ret
|
|
|
|
dec_delay_counter:
|
|
000152 503a subi delay_counter_r, 10
|
|
000153 3238 cpi delay_counter_r, 40
|
|
000154 f008 brlo _reset_counter
|
|
000155 9508 ret
|
|
_reset_counter:
|
|
000156 ef3f ldi delay_counter_r, 0xff
|
|
000157 9508 ret
|
|
|
|
effect_1: ; Shift bits of an leds in port every 50ms
|
|
000158 931f push r17
|
|
000159 932f push r18
|
|
00015a 933f push r19
|
|
00015b 934f push r20
|
|
|
|
00015c 94f8 cli
|
|
00015d b34b in r20, LED_PORT
|
|
|
|
00015e 930f
|
|
00015f ef01
|
|
000160 bb0b
|
|
000161 910f outi LED_PORT, 0xf1
|
|
000162 d084 rcall delay_50ms
|
|
000163 e011 ldi r17, 0x01
|
|
000164 e033 ldi r19, 3
|
|
|
|
; shift bits to left loop
|
|
_eff_1_shift_l:
|
|
000165 ef20 ldi r18, 0xf0
|
|
000166 0f11 lsl r17
|
|
000167 0f21 add r18, r17
|
|
000168 bb2b out LED_PORT, r18
|
|
000169 d07d rcall delay_50ms
|
|
00016a 953a dec r19
|
|
00016b f7c9 brne _eff_1_shift_l
|
|
|
|
00016c 930f
|
|
00016d ef08
|
|
00016e bb0b
|
|
00016f 910f outi LED_PORT, 0xf8
|
|
000170 d076 rcall delay_50ms
|
|
000171 e018 ldi r17, 0x08
|
|
000172 e033 ldi r19, 3
|
|
|
|
; shift bits to right loop
|
|
_eff_1_shift_r:
|
|
000173 ef20 ldi r18, 0xf0
|
|
000174 9516 lsr r17
|
|
000175 0f21 add r18, r17
|
|
000176 bb2b out LED_PORT, r18
|
|
000177 d06f rcall delay_50ms
|
|
000178 953a dec r19
|
|
000179 f7c9 brne _eff_1_shift_r
|
|
|
|
00017a 9478 sei
|
|
|
|
; out saved PORT values
|
|
00017b bb4b out LED_PORT, r20
|
|
00017c 914f pop r20
|
|
00017d 913f pop r19
|
|
00017e 912f pop r18
|
|
00017f 911f pop r17
|
|
000180 9508 ret
|
|
|
|
effect_2:
|
|
000181 930f
|
|
000182 e80e
|
|
000183 bf06
|
|
000184 910f outi OCR0A, 142
|
|
000185 9ad8 sbi LED_PORT, 0
|
|
000186 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
000187 d05f rcall delay_50ms
|
|
000188 d05e rcall delay_50ms
|
|
000189 98d8 cbi LED_PORT, 0
|
|
00018a 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
|
|
00018b 930f
|
|
00018c e609
|
|
00018d bf06
|
|
00018e 910f outi OCR0A, 105
|
|
00018f 9ad9 sbi LED_PORT, 1
|
|
000190 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
000191 d055 rcall delay_50ms
|
|
000192 d054 rcall delay_50ms
|
|
000193 98d9 cbi LED_PORT, 1
|
|
000194 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
|
|
000195 930f
|
|
000196 e500
|
|
000197 bf06
|
|
000198 910f outi OCR0A, 80
|
|
000199 9ada sbi LED_PORT, 2
|
|
00019a 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
00019b d04b rcall delay_50ms
|
|
00019c d04a rcall delay_50ms
|
|
00019d 98da cbi LED_PORT, 2
|
|
00019e 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
|
|
00019f 930f
|
|
0001a0 e407
|
|
0001a1 bf06
|
|
0001a2 910f outi OCR0A, 71
|
|
0001a3 9adb sbi LED_PORT, 3
|
|
0001a4 9aba sbi BUZZ_DIR, BUZZ_PIN
|
|
0001a5 d041 rcall delay_50ms
|
|
0001a6 d040 rcall delay_50ms
|
|
0001a7 98db cbi LED_PORT, 3
|
|
0001a8 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
0001a9 9508 ret
|
|
|
|
init_interrupts:
|
|
; enable Port Change Interrupt
|
|
0001aa e100 ldi temp_r, (1<<PCIE0)
|
|
0001ab bf0b out GIMSK, temp_r
|
|
|
|
; set Pin Change Mask Register
|
|
0001ac ef00 ldi temp_r, (1<<PCINT4) | (1<<PCINT5)| (1<<PCINT6) | (1<<PCINT7)
|
|
0001ad bb02 out PCMSK0, temp_r
|
|
|
|
0001ae 2700 clr temp_r
|
|
0001af 9508 ret
|
|
|
|
init_buzzer:
|
|
0001b0 98ba cbi BUZZ_DIR, BUZZ_PIN
|
|
|
|
; setup timer
|
|
0001b1 e402 ldi temp_r, (1<<COM0A0) | (1<<WGM01)
|
|
; set CTC timer mode and toggle OC0A pin on Compare Match
|
|
0001b2 bf00 out TCCR0A, temp_r
|
|
|
|
0001b3 ef0f ldi temp_r, 255
|
|
0001b4 bf06 out OCR0A, temp_r
|
|
|
|
0001b5 e002 ldi temp_r, (1<<CS01)
|
|
; prescale on 8
|
|
0001b6 bf03 out TCCR0B, temp_r
|
|
|
|
0001b7 e001 ldi temp_r, (1<<TOIE0)
|
|
; enable Timer/Counter0 Overflow Interrupt
|
|
0001b8 bf09 out TIMSK0, temp_r
|
|
0001b9 9508 ret
|
|
|
|
init_ports: ; Init MCU ports
|
|
; setup PORTA
|
|
0001ba e00f ldi temp_r, 0x0f
|
|
; set directions of leds and buttons
|
|
0001bb bb0a out DDRA, temp_r
|
|
0001bc 9502 swap temp_r
|
|
; set low signal on leds and pull-up on buttons
|
|
0001bd bb0b out PORTA, temp_r
|
|
|
|
; setup PORTB
|
|
0001be 9aba sbi DDRB, BUZZ_PIN ; Set direction of buzzer pin to output
|
|
0001bf 98c2 cbi PORTB, BUZZ_PIN ; Set low signal on buzzer
|
|
0001c0 9508 ret
|
|
|
|
init_sm:
|
|
0001c1 b705 in temp_r, MCUCR
|
|
0001c2 6100 ori temp_r, (1<<SM1)
|
|
; config sleep mode to power-down
|
|
0001c3 bf05 out MCUCR, temp_r
|
|
0001c4 9508 ret
|
|
|
|
init_wdt:
|
|
0001c5 94f8 cli
|
|
0001c6 95a8 wdr
|
|
|
|
0001c7 b501 in temp_r, WDTCSR
|
|
0001c8 6108 ori temp_r, (1<<WDCE) | (1<<WDE)
|
|
; allow changing the watchdog bits and enable watchdog
|
|
0001c9 bd01 out WDTCSR, temp_r
|
|
|
|
0001ca e40d ldi temp_r, (1<<WDE) | (1<<WDIE) | (1<<WDP2) | (1<<WDP0)
|
|
; config watchdog to interrupt mode and setup prescaler (0.5 sec)
|
|
0001cb bd01 out WDTCSR, temp_r
|
|
0001cc 9478 sei
|
|
0001cd 9508 ret
|
|
|
|
delay: ; For 1MHz frequency
|
|
0001ce 932f push r18
|
|
0001cf 934f push r20
|
|
0001d0 ef2f ldi r18, 255
|
|
0001d1 2f43 mov r20, delay_counter_r
|
|
_delay_loop:
|
|
0001d2 0000 nop
|
|
0001d3 952a dec r18
|
|
0001d4 f7e9 brne _delay_loop
|
|
0001d5 0000 nop
|
|
0001d6 954a dec r20
|
|
0001d7 f7d1 brne _delay_loop
|
|
0001d8 0000 nop
|
|
0001d9 914f pop r20
|
|
0001da 912f pop r18
|
|
0001db 9508 ret
|
|
|
|
delay_20ms:
|
|
0001dc 932f push r18
|
|
0001dd 933f push r19
|
|
|
|
0001de e12a ldi r18, 26
|
|
0001df ef39 ldi r19, 249
|
|
_loop_d_20ms:
|
|
0001e0 953a dec r19
|
|
0001e1 f7f1 brne _loop_d_20ms
|
|
0001e2 952a dec r18
|
|
0001e3 f7e1 brne _loop_d_20ms
|
|
0001e4 913f pop r19
|
|
0001e5 912f pop r18
|
|
0001e6 9508 ret
|
|
|
|
delay_50ms: ; For 1MHz frequency
|
|
0001e7 932f push r18
|
|
0001e8 933f push r19
|
|
|
|
0001e9 e421 ldi r18, 65
|
|
0001ea ee3f ldi r19, 239
|
|
_loop_d_50ms:
|
|
0001eb 953a dec r19
|
|
0001ec f7f1 brne _loop_d_50ms
|
|
0001ed 952a dec r18
|
|
0001ee f7e1 brne _loop_d_50ms
|
|
0001ef 0000 nop
|
|
0001f0 913f pop r19
|
|
0001f1 912f pop r18
|
|
0001f2 9508 ret
|
|
|
|
|
|
delay_1s: ; For 1MHz frequency
|
|
0001f3 938f push r24
|
|
0001f4 939f push r25
|
|
|
|
.equ outer_count = 100
|
|
.equ inner_count = 2499
|
|
|
|
0001f5 e624 ldi r18, outer_count
|
|
_reset:
|
|
0001f6 ec83 ldi r24, low(inner_count)
|
|
0001f7 e099 ldi r25, high(inner_count)
|
|
_loop:
|
|
0001f8 9701 sbiw r24, 1
|
|
0001f9 f7f1 brne _loop
|
|
0001fa 952a dec r18
|
|
0001fb f7d1 brne _reset
|
|
0001fc e624 ldi r18, outer_count
|
|
0001fd 919f pop r25
|
|
0001fe 918f pop r24
|
|
0001ff 9508 ret
|
|
|
|
000200 654d
|
|
000201 6f6d
|
|
000202 7972
|
|
000203 6c20
|
|
000204 6465
|
|
000205 6720
|
|
000206 6d61
|
|
000207 2e65
|
|
000208 5720
|
|
000209 6972
|
|
00020a 7474
|
|
00020b 6e65
|
|
00020c 6220
|
|
00020d 2079
|
|
00020e 6553
|
|
00020f 6772
|
|
000210 7965
|
|
000211 5920
|
|
000212 7261
|
|
000213 6f6b
|
|
000214 2076
|
|
000215 3732
|
|
000216 302e
|
|
000217 2e39
|
|
000218 3032
|
|
|
|
|
|
RESOURCE USE INFORMATION
|
|
------------------------
|
|
|
|
Notice:
|
|
The register and instruction counts are symbol table hit counts,
|
|
and hence implicitly used resources are not counted, eg, the
|
|
'lpm' instruction without operands implicitly uses r0 and z,
|
|
none of which are counted.
|
|
|
|
x,y,z are separate entities in the symbol table and are
|
|
counted separately from r26..r31 here.
|
|
|
|
.dseg memory usage only counts static data declared with .byte
|
|
|
|
"ATtiny24A" register use summary:
|
|
x : 0 y : 2 z : 1 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
|
|
r5 : 0 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 6 r11: 4 r12: 0
|
|
r13: 0 r14: 0 r15: 0 r16: 115 r17: 23 r18: 44 r19: 20 r20: 12
|
|
r21: 4 r22: 5 r23: 18 r24: 6 r25: 6 r26: 28 r27: 0 r28: 2
|
|
r29: 2 r30: 2 r31: 2
|
|
Registers used: 19 out of 35 (54.3%)
|
|
|
|
"ATtiny24A" instruction use summary:
|
|
.lds : 0 .sts : 0 adc : 0 add : 3 adiw : 0 and : 0
|
|
andi : 3 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
|
|
brcc : 0 brcs : 0 break : 0 breq : 6 brge : 0 brhc : 0
|
|
brhs : 0 brid : 0 brie : 0 brlo : 5 brlt : 0 brmi : 0
|
|
brne : 22 brpl : 0 brsh : 1 brtc : 0 brts : 0 brvc : 0
|
|
brvs : 0 bset : 0 bst : 0 cbi : 28 cbr : 1 clc : 0
|
|
clh : 0 cli : 4 cln : 0 clr : 10 cls : 0 clt : 0
|
|
clv : 0 clz : 0 com : 0 cp : 3 cpc : 0 cpi : 20
|
|
cpse : 0 dec : 13 eor : 1 icall : 0 ijmp : 0 in : 12
|
|
inc : 3 ld : 2 ldd : 0 ldi : 65 lds : 6 lpm : 0
|
|
lsl : 1 lsr : 1 mov : 8 movw : 0 neg : 0 nop : 5
|
|
or : 0 ori : 4 out : 40 pop : 37 push : 35 rcall : 51
|
|
ret : 24 reti : 16 rjmp : 18 rol : 0 ror : 0 sbc : 0
|
|
sbci : 0 sbi : 25 sbic : 0 sbis : 0 sbiw : 1 sbr : 1
|
|
sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 4 sen : 0
|
|
ser : 0 ses : 0 set : 0 sev : 0 sez : 0 sleep : 1
|
|
spm : 0 st : 1 std : 0 sts : 10 sub : 0 subi : 1
|
|
swap : 2 tst : 0 wdr : 2
|
|
Instructions used: 41 out of 105 (39.0%)
|
|
|
|
"ATtiny24A" memory use summary [bytes]:
|
|
Segment Begin End Code Data Used Size Use%
|
|
---------------------------------------------------------------
|
|
[.cseg] 0x000000 0x000434 1024 52 1076 2048 52.5%
|
|
[.dseg] 0x000060 0x000063 0 3 3 128 2.3%
|
|
[.eseg] 0x000000 0x000000 0 0 0 128 0.0%
|
|
|
|
Assembly complete, 0 errors, 1 warnings
|