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Sergey Yarkov 2023-10-06 19:34:50 +03:00
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113
Makefile Normal file
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#
# There exist several targets which are by default empty and which can be
# used for execution of your targets. These targets are usually executed
# before and after some main targets. They are:
#
# .build-pre: called before 'build' target
# .build-post: called after 'build' target
# .clean-pre: called before 'clean' target
# .clean-post: called after 'clean' target
# .clobber-pre: called before 'clobber' target
# .clobber-post: called after 'clobber' target
# .all-pre: called before 'all' target
# .all-post: called after 'all' target
# .help-pre: called before 'help' target
# .help-post: called after 'help' target
#
# Targets beginning with '.' are not intended to be called on their own.
#
# Main targets can be executed directly, and they are:
#
# build build a specific configuration
# clean remove built files from a configuration
# clobber remove all built files
# all build all configurations
# help print help mesage
#
# Targets .build-impl, .clean-impl, .clobber-impl, .all-impl, and
# .help-impl are implemented in nbproject/makefile-impl.mk.
#
# Available make variables:
#
# CND_BASEDIR base directory for relative paths
# CND_DISTDIR default top distribution directory (build artifacts)
# CND_BUILDDIR default top build directory (object files, ...)
# CONF name of current configuration
# CND_ARTIFACT_DIR_${CONF} directory of build artifact (current configuration)
# CND_ARTIFACT_NAME_${CONF} name of build artifact (current configuration)
# CND_ARTIFACT_PATH_${CONF} path to build artifact (current configuration)
# CND_PACKAGE_DIR_${CONF} directory of package (current configuration)
# CND_PACKAGE_NAME_${CONF} name of package (current configuration)
# CND_PACKAGE_PATH_${CONF} path to package (current configuration)
#
# NOCDDL
# Environment
MKDIR=mkdir
CP=cp
CCADMIN=CCadmin
RANLIB=ranlib
# build
build: .build-post
.build-pre:
# Add your pre 'build' code here...
.build-post: .build-impl
# Add your post 'build' code here...
# clean
clean: .clean-post
.clean-pre:
# Add your pre 'clean' code here...
# WARNING: the IDE does not call this target since it takes a long time to
# simply run make. Instead, the IDE removes the configuration directories
# under build and dist directly without calling make.
# This target is left here so people can do a clean when running a clean
# outside the IDE.
.clean-post: .clean-impl
# Add your post 'clean' code here...
# clobber
clobber: .clobber-post
.clobber-pre:
# Add your pre 'clobber' code here...
.clobber-post: .clobber-impl
# Add your post 'clobber' code here...
# all
all: .all-post
.all-pre:
# Add your pre 'all' code here...
.all-post: .all-impl
# Add your post 'all' code here...
# help
help: .help-post
.help-pre:
# Add your pre 'help' code here...
.help-post: .help-impl
# Add your post 'help' code here...
# include project implementation makefile
include nbproject/Makefile-impl.mk
# include project make variables
include nbproject/Makefile-variables.mk

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.DEF cycles = r5
.DEF t1 = r16
.DEF t2 = r17
.DEF t3 = r18
.DEF timer_secs = r19
.EQU ROAD_R_LED = PB0
.EQU ROAD_Y_LED = PB1
.EQU ROAD_G_LED = PB2
.EQU WALK_R_LED = PB3
.EQU WALK_G_LED = PB4
.EQU LED_DIR = DDRB
.EQU LED_PORT = PORTB
.EQU MAX_CYCLES = 2
.EQU TIMER1_PRESCALE_MASK = 0x0f ; 16384

22
dist/default/production/attiny45v_traffic-lights.X.production.hex vendored Normal file
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dist/default/production/attiny45v_traffic-lights.X.production.lss vendored Normal file
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AVRASM ver. 2.2.7 firmware.asm Fri Oct 06 19:23:41 2023
[builtin](2): Including file '/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn45def.inc'
firmware.asm(19): Including file 'definitions.asm'
[builtin](2): Including file '/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn45def.inc'
firmware.asm(19): Including file 'definitions.asm'
; Project name: Traffic Lights
;***** Created: 2011-02-09 12:04 ******* Source: ATtiny45.xml ************
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "tn45def.inc"
;* Title : Register/Bit Definitions for the ATtiny45
;* Date : 2011-02-09
;* Version : 2.35
;* Support E-mail : avr@atmel.com
;* Target MCU : ATtiny45
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _TN45DEF_INC_
#define _TN45DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATtiny45
#pragma AVRPART ADMIN PART_NAME ATtiny45
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x92
.equ SIGNATURE_002 = 0x06
#pragma AVRPART CORE CORE_VERSION V2
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ GIMSK = 0x3b
.equ GIFR = 0x3a
.equ TIMSK = 0x39
.equ TIFR = 0x38
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ TCCR0B = 0x33
.equ TCNT0 = 0x32
.equ OSCCAL = 0x31
.equ TCCR1 = 0x30
.equ TCNT1 = 0x2f
.equ OCR1A = 0x2e
.equ OCR1C = 0x2d
.equ GTCCR = 0x2c
.equ OCR1B = 0x2b
.equ TCCR0A = 0x2a
.equ OCR0A = 0x29
.equ OCR0B = 0x28
.equ PLLCSR = 0x27
.equ CLKPR = 0x26
.equ DT1A = 0x25
.equ DT1B = 0x24
.equ DTPS = 0x23
.equ DWDR = 0x22
.equ WDTCR = 0x21
.equ PRR = 0x20
.equ EEARH = 0x1f
.equ EEARL = 0x1e
.equ EEDR = 0x1d
.equ EECR = 0x1c
.equ PORTB = 0x18
.equ DDRB = 0x17
.equ PINB = 0x16
.equ PCMSK = 0x15
.equ DIDR0 = 0x14
.equ GPIOR2 = 0x13
.equ GPIOR1 = 0x12
.equ GPIOR0 = 0x11
.equ USIBR = 0x10
.equ USIDR = 0x0f
.equ USISR = 0x0e
.equ USICR = 0x0d
.equ ACSR = 0x08
.equ ADMUX = 0x07
.equ ADCSRA = 0x06
.equ ADCH = 0x05
.equ ADCL = 0x04
.equ ADCSRB = 0x03
; ***** BIT DEFINITIONS **************************************************
; ***** PORTB ************************
; PORTB - Data Register, Port B
.equ PORTB0 = 0 ;
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ;
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ;
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ;
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ;
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ;
.equ PB5 = 5 ; For compatibility
; DDRB - Data Direction Register, Port B
.equ DDB0 = 0 ;
.equ DDB1 = 1 ;
.equ DDB2 = 2 ;
.equ DDB3 = 3 ;
.equ DDB4 = 4 ;
.equ DDB5 = 5 ;
; PINB - Input Pins, Port B
.equ PINB0 = 0 ;
.equ PINB1 = 1 ;
.equ PINB2 = 2 ;
.equ PINB3 = 3 ;
.equ PINB4 = 4 ;
.equ PINB5 = 5 ;
; ***** ANALOG_COMPARATOR ************
; ADCSRB - ADC Control and Status Register B
.equ ACME = 6 ; Analog Comparator Multiplexer Enable
; ACSR - Analog Comparator Control And Status Register
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
.equ ACIE = 3 ; Analog Comparator Interrupt Enable
.equ ACI = 4 ; Analog Comparator Interrupt Flag
.equ ACO = 5 ; Analog Compare Output
.equ ACBG = 6 ; Analog Comparator Bandgap Select
.equ AINBG = ACBG ; For compatibility
.equ ACD = 7 ; Analog Comparator Disable
; DIDR0 -
.equ AIN0D = 0 ; AIN0 Digital Input Disable
.equ AIN1D = 1 ; AIN1 Digital Input Disable
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ REFS2 = 4 ; Reference Selection Bit 2
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; ADCSRB - ADC Control and Status Register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
.equ IPR = 5 ; Input Polarity Mode
.equ BIN = 7 ; Bipolar Input Mode
; DIDR0 - Digital Input Disable Register 0
.equ ADC1D = 2 ; ADC1 Digital input Disable
.equ ADC3D = 3 ; ADC3 Digital input Disable
.equ ADC2D = 4 ; ADC2 Digital input Disable
.equ ADC0D = 5 ; ADC0 Digital input Disable
; ***** USI **************************
; USIBR - USI Buffer Register
.equ USIBR0 = 0 ; USI Buffer Register bit 0
.equ USIBR1 = 1 ; USI Buffer Register bit 1
.equ USIBR2 = 2 ; USI Buffer Register bit 2
.equ USIBR3 = 3 ; USI Buffer Register bit 3
.equ USIBR4 = 4 ; USI Buffer Register bit 4
.equ USIBR5 = 5 ; USI Buffer Register bit 5
.equ USIBR6 = 6 ; USI Buffer Register bit 6
.equ USIBR7 = 7 ; USI Buffer Register bit 7
; USIDR - USI Data Register
.equ USIDR0 = 0 ; USI Data Register bit 0
.equ USIDR1 = 1 ; USI Data Register bit 1
.equ USIDR2 = 2 ; USI Data Register bit 2
.equ USIDR3 = 3 ; USI Data Register bit 3
.equ USIDR4 = 4 ; USI Data Register bit 4
.equ USIDR5 = 5 ; USI Data Register bit 5
.equ USIDR6 = 6 ; USI Data Register bit 6
.equ USIDR7 = 7 ; USI Data Register bit 7
; USISR - USI Status Register
.equ USICNT0 = 0 ; USI Counter Value Bit 0
.equ USICNT1 = 1 ; USI Counter Value Bit 1
.equ USICNT2 = 2 ; USI Counter Value Bit 2
.equ USICNT3 = 3 ; USI Counter Value Bit 3
.equ USIDC = 4 ; Data Output Collision
.equ USIPF = 5 ; Stop Condition Flag
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag
.equ USISIF = 7 ; Start Condition Interrupt Flag
; USICR - USI Control Register
.equ USITC = 0 ; Toggle Clock Port Pin
.equ USICLK = 1 ; Clock Strobe
.equ USICS0 = 2 ; USI Clock Source Select Bit 0
.equ USICS1 = 3 ; USI Clock Source Select Bit 1
.equ USIWM0 = 4 ; USI Wire Mode Bit 0
.equ USIWM1 = 5 ; USI Wire Mode Bit 1
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable
.equ USISIE = 7 ; Start Condition Interrupt Enable
; ***** EXTERNAL_INTERRUPT ***********
; MCUCR - MCU Control Register
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
; GIMSK - General Interrupt Mask Register
.equ GICR = GIMSK ; For compatibility
.equ PCIE = 5 ; Pin Change Interrupt Enable
.equ INT0 = 6 ; External Interrupt Request 0 Enable
; GIFR - General Interrupt Flag register
.equ PCIF = 5 ; Pin Change Interrupt Flag
.equ INTF0 = 6 ; External Interrupt Flag 0
; PCMSK - Pin Change Enable Mask
.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0
.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1
.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2
.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3
.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4
.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5
; ***** EEPROM ***********************
; EEARL - EEPROM Address Register Low Byte
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
; EEARH - EEPROM Address Register High Byte
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
; ***** WATCHDOG *********************
; WDTCR - Watchdog Timer Control Register
.equ WDTCSR = WDTCR ; For compatibility
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDTOE = WDCE ; For compatibility
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** TIMER_COUNTER_0 **************
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable
.equ OCIE0A = 4 ; Timer/Counter0 Output Compare Match A Interrupt Enable
; TIFR - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B
.equ OCF0A = 4 ; Timer/Counter0 Output Compare Flag 0A
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
; OCR0B - Timer/Counter0 Output Compare Register
;.equ OCR0_0 = 0 ;
;.equ OCR0_1 = 1 ;
;.equ OCR0_2 = 2 ;
;.equ OCR0_3 = 3 ;
;.equ OCR0_4 = 4 ;
;.equ OCR0_5 = 5 ;
;.equ OCR0_6 = 6 ;
;.equ OCR0_7 = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSR0 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TCCR1 - Timer/Counter Control Register
.equ CS10 = 0 ; Clock Select Bits
.equ CS11 = 1 ; Clock Select Bits
.equ CS12 = 2 ; Clock Select Bits
.equ CS13 = 3 ; Clock Select Bits
.equ COM1A0 = 4 ; Compare Output Mode, Bit 1
.equ COM1A1 = 5 ; Compare Output Mode, Bit 0
.equ PWM1A = 6 ; Pulse Width Modulator Enable
.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match
; TCNT1 - Timer/Counter Register
.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0
.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1
.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2
.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3
.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4
.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5
.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6
.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7
; OCR1A - Output Compare Register
.equ OCR1A0 = 0 ; Output Compare Register A Bit 0
.equ OCR1A1 = 1 ; Output Compare Register A Bit 1
.equ OCR1A2 = 2 ; Output Compare Register A Bit 2
.equ OCR1A3 = 3 ; Output Compare Register A Bit 3
.equ OCR1A4 = 4 ; Output Compare Register A Bit 4
.equ OCR1A5 = 5 ; Output Compare Register A Bit 5
.equ OCR1A6 = 6 ; Output Compare Register A Bit 6
.equ OCR1A7 = 7 ; Output Compare Register A Bit 7
; OCR1B - Output Compare Register
.equ OCR1B0 = 0 ; Output Compare Register B Bit 0
.equ OCR1B1 = 1 ; Output Compare Register B Bit 1
.equ OCR1B2 = 2 ; Output Compare Register B Bit 2
.equ OCR1B3 = 3 ; Output Compare Register B Bit 3
.equ OCR1B4 = 4 ; Output Compare Register B Bit 4
.equ OCR1B5 = 5 ; Output Compare Register B Bit 5
.equ OCR1B6 = 6 ; Output Compare Register B Bit 6
.equ OCR1B7 = 7 ; Output Compare Register B Bit 7
; OCR1C - Output compare register
.equ OCR1C0 = 0 ;
.equ OCR1C1 = 1 ;
.equ OCR1C2 = 2 ;
.equ OCR1C3 = 3 ;
.equ OCR1C4 = 4 ;
.equ OCR1C5 = 5 ;
.equ OCR1C6 = 6 ;
.equ OCR1C7 = 7 ;
; TIMSK - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1B = 5 ; OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
.equ OCIE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
; TIFR - Timer/Counter Interrupt Flag Register
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B
.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A
; GTCCR - Timer counter control register
.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1
.equ FOC1A = 2 ; Force Output Compare 1A
.equ FOC1B = 3 ; Force Output Compare Match 1B
.equ COM1B0 = 4 ; Comparator B Output Mode
.equ COM1B1 = 5 ; Comparator B Output Mode
.equ PWM1B = 6 ; Pulse Width Modulator B Enable
; DTPS - Dead time prescaler register
.equ DTPS0 = 0 ;
.equ DTPS1 = 1 ;
; DT1A - Dead time value register
.equ DTVL0 = 0 ;
.equ DTVL1 = 1 ;
.equ DTVL2 = 2 ;
.equ DTVL3 = 3 ;
.equ DTVH0 = 4 ;
.equ DTVH1 = 5 ;
.equ DTVH2 = 6 ;
.equ DTVH3 = 7 ;
; DT1B - Dead time value B
;.equ DTVL0 = 0 ;
;.equ DTVL1 = 1 ;
;.equ DTVL2 = 2 ;
;.equ DTVL3 = 3 ;
;.equ DTVH0 = 4 ;
;.equ DTVH1 = 5 ;
;.equ DTVH2 = 6 ;
;.equ DTVH3 = 7 ;
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
;.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
;.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
.equ BODSE = 2 ; BOD Sleep Enable
.equ SM0 = 3 ; Sleep Mode Select Bit 0
.equ SM1 = 4 ; Sleep Mode Select Bit 1
.equ SE = 5 ; Sleep Enable
.equ PUD = 6 ; Pull-up Disable
.equ BODS = 7 ; BOD Sleep
; MCUSR - MCU Status register
.equ PORF = 0 ; Power-On Reset Flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
; PRR - Power Reduction Register
.equ PRADC = 0 ; Power Reduction ADC
.equ PRUSI = 1 ; Power Reduction USI
.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
; OSCCAL - Oscillator Calibration Register
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
.equ CAL7 = 7 ; Oscillatro Calibration Value Bit 7
; PLLCSR - PLL Control and status register
.equ PLOCK = 0 ; PLL Lock detector
.equ PLLE = 1 ; PLL Enable
.equ PCKE = 2 ; PCK Enable
.equ LSM = 7 ; Low speed mode
; CLKPR - Clock Prescale Register
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
.equ CLKPCE = 7 ; Clock Prescaler Change Enable
; DWDR - debugWire data register
.equ DWDR0 = 0 ;
.equ DWDR1 = 1 ;
.equ DWDR2 = 2 ;
.equ DWDR3 = 3 ;
.equ DWDR4 = 4 ;
.equ DWDR5 = 5 ;
.equ DWDR6 = 6 ;
.equ DWDR7 = 7 ;
; GPIOR2 - General Purpose IO register 2
.equ GPIOR20 = 0 ;
.equ GPIOR21 = 1 ;
.equ GPIOR22 = 2 ;
.equ GPIOR23 = 3 ;
.equ GPIOR24 = 4 ;
.equ GPIOR25 = 5 ;
.equ GPIOR26 = 6 ;
.equ GPIOR27 = 7 ;
; GPIOR1 - General Purpose register 1
.equ GPIOR10 = 0 ;
.equ GPIOR11 = 1 ;
.equ GPIOR12 = 2 ;
.equ GPIOR13 = 3 ;
.equ GPIOR14 = 4 ;
.equ GPIOR15 = 5 ;
.equ GPIOR16 = 6 ;
.equ GPIOR17 = 7 ;
; GPIOR0 - General purpose register 0
.equ GPIOR00 = 0 ;
.equ GPIOR01 = 1 ;
.equ GPIOR02 = 2 ;
.equ GPIOR03 = 3 ;
.equ GPIOR04 = 4 ;
.equ GPIOR05 = 5 ;
.equ GPIOR06 = 6 ;
.equ GPIOR07 = 7 ;
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ RFLB = 3 ; Read fuse and lock bits
.equ CTPB = 4 ; Clear temporary page buffer
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lockbit
.equ LB2 = 1 ; Lockbit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock source
.equ CKSEL1 = 1 ; Select Clock source
.equ CKSEL2 = 2 ; Select Clock source
.equ CKSEL3 = 3 ; Select Clock source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ CKOUT = 6 ; Clock Output Enable
.equ CKDIV8 = 7 ; Divide clock by 8
; HIGH fuse bits
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase
.equ WDTON = 4 ; Watchdog Timer always on
.equ SPIEN = 5 ; Enable Serial Program and Data Downloading
.equ DWEN = 6 ; DebugWIRE Enable
.equ RSTDISBL = 7 ; External Reset disable
; EXTENDED fuse bits
.equ SELFPRGEN = 0 ; Self-Programming Enable
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x07ff ; Note: Word address
.equ IOEND = 0x003f
.equ SRAM_START = 0x0060
.equ SRAM_SIZE = 256
.equ RAMEND = 0x015f
.equ XRAMEND = 0x0000
.equ E2END = 0x00ff
.equ EEPROMEND = 0x00ff
.equ EEADRBITS = 8
#pragma AVRPART MEMORY PROG_FLASH 4096
#pragma AVRPART MEMORY EEPROM 256
#pragma AVRPART MEMORY INT_SRAM SIZE 256
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x0
.equ NRWW_STOP_ADDR = 0x7ff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x0
.equ PAGESIZE = 32
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0001 ; External Interrupt 0
.equ PCI0addr = 0x0002 ; Pin change Interrupt Request 0
.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A
.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow
.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow
.equ ERDYaddr = 0x0006 ; EEPROM Ready
.equ ACIaddr = 0x0007 ; Analog comparator
.equ ADCCaddr = 0x0008 ; ADC Conversion ready
.equ OC1Baddr = 0x0009 ; Timer/Counter1 Compare Match B
.equ OC0Aaddr = 0x000a ; Timer/Counter0 Compare Match A
.equ OC0Baddr = 0x000b ; Timer/Counter0 Compare Match B
.equ WDTaddr = 0x000c ; Watchdog Time-out
.equ USI_STARTaddr = 0x000d ; USI START
.equ USI_OVFaddr = 0x000e ; USI Overflow
.equ INT_VECTORS_SIZE = 15 ; size in words
#endif /* _TN45DEF_INC_ */
; ***** END OF FILE ******************************************************
; Description: Simple program of traffic lights on AVR microcontroller.
; Source code: https://github.com/sergeyyarkov/attiny24a_traffic-lights
; Device: ATtiny45v
; Assembler: AVR macro assembler 2.2.7
; Clock frequency: 1MHz
; Fuses: lfuse: , hfuse: , efuse: , lock:
;
; Written by Sergey Yarkov 06.10.2023
; CPU Clock Freq = 1MHz (with CKDIV8)
; Timer prescaler = Fsyc / 16384
; Freq(t) = 1MHz / 16384 = 61.03515625 Hz
; Tick(t) = 1 / Freq(t) = 1 / 61.03515625 = 16384 uS (0.016384 sec)
; SumTicks = 1 sec / 0.016384 sec = 61
.LIST
.INCLUDE "definitions.asm"
.DEF t1 = r16
.DEF t2 = r17
.DEF t3 = r18
.DEF timer_secs = r19
.EQU ROAD_R_LED = PB0
.EQU ROAD_Y_LED = PB1
.EQU ROAD_G_LED = PB2
.EQU WALK_R_LED = PB3
.EQU WALK_G_LED = PB4
.EQU LED_DIR = DDRB
.EQU LED_PORT = PORTB
.EQU MAX_CYCLES = 2
.MACRO stsi
ldi t1, @1
sts @0, t1
.ENDMACRO
.DSEG
.ORG SRAM_START
000060 STATE: .BYTE 1
.CSEG
.ORG 0x00
000000 c003 rjmp RESET_vect
.ORG 0x03
000003 c075 rjmp TIMER1_COMPA
RESET_vect:
000004 e50f ldi t1, LOW(RAMEND)
000005 bf0d out SPL, t1
INIT:
000006 e10f ldi t1, (1<<ROAD_R_LED) | (1<<ROAD_Y_LED) | (1<<ROAD_G_LED) | (1<<WALK_R_LED) | (1<<WALK_G_LED)
000007 bb07 out DDRB, t1
000008 2700 clr t1
000009 bb08 out LED_PORT, t1
; Setup 8-bit timer-1 in CTC mode
00000a e800 ldi t1, (1<<CTC1)
00000b bf00 out TCCR1, t1 ; setup timer
00000c 2700 clr t1 ; clear timer counter register
00000d bd0f out TCNT1, t1
00000e e30d ldi t1, 61
00000f bd0e out OCR1A, t1
000010 e400 ldi t1, (1<<OCIE1A) ; enable output compare A interrupt
000011 bf09 out TIMSK, t1
; Setup sleep mode in power-down
000012 b705 in t1, MCUCR
000013 6100 ori t1, (1<<SM1)
000014 bf05 out MCUCR, t1
000015 2455 clr cycles
000016 e000
000017 9300 0060 stsi STATE, 0
000019 9478 sei
LOOP:
00001a 9120 0060 lds t3, STATE
_S0: ; State 0
00001c 3020 cpi t3, 0
00001d f469 brne _S1
00001e 9ac4 sbi LED_PORT, WALK_G_LED
00001f 9ac0 sbi LED_PORT, ROAD_R_LED
000020 d069 rcall TIMER_ON
000021 3035 cpi timer_secs, 5
000022 f009 breq _S0_TIMER
000023 c04e rjmp END
_S0_TIMER:
000024 98c0 cbi LED_PORT, ROAD_R_LED
000025 e001
000026 9300 0060 stsi STATE, 1
000028 d05a rcall TIMER_OFF
000029 94e8 clt
00002a c047 rjmp END
_S1: ; State 1
00002b 3021 cpi t3, 1
00002c f489 brne _S2
00002d d05c rcall TIMER_ON
00002e 3032 cpi timer_secs, 2
00002f f029 breq _S1_TIMER
000030 9ac0 sbi LED_PORT, ROAD_R_LED
000031 d05c rcall DELAY
000032 98c0 cbi LED_PORT, ROAD_R_LED
000033 d05a rcall DELAY
000034 c03d rjmp END
_S1_TIMER:
000035 98c1 cbi LED_PORT, ROAD_Y_LED
000036 2d05 mov t1, cycles
000037 3002 cpi t1, MAX_CYCLES
000038 f5d4 brge MCU_SLEEP
000039 e002
00003a 9300 0060 stsi STATE, 2
00003c d046 rcall TIMER_OFF
00003d c034 rjmp END
_S2: ; State 2
00003e 3022 cpi t3, 2
00003f f4a9 brne _S3
000040 9ac1 sbi LED_PORT, ROAD_Y_LED
000041 d048 rcall TIMER_ON
000042 3032 cpi timer_secs, 2
000043 f009 breq _S2_TIMER
000044 c02d rjmp END
_S2_TIMER:
000045 98c1 cbi LED_PORT, ROAD_Y_LED
000046 f00e brts _CYCLE_DONE
000047 c006 rjmp _S2_NEXT
_CYCLE_DONE:
000048 98c3 cbi LED_PORT, WALK_R_LED
000049 9453 inc cycles
00004a e000
00004b 9300 0060 stsi STATE, 0
00004d c024 rjmp END
_S2_NEXT:
00004e 98c4 cbi LED_PORT, WALK_G_LED
00004f 9ac3 sbi LED_PORT, WALK_R_LED
000050 e003
000051 9300 0060 stsi STATE, 3
000053 d02f rcall TIMER_OFF
000054 c01d rjmp END
_S3: ; State 3
000055 3023 cpi t3, 3
000056 f459 brne _S4
000057 9ac2 sbi LED_PORT, ROAD_G_LED
000058 d031 rcall TIMER_ON
000059 3035 cpi timer_secs, 5
00005a f009 breq _S3_TIMER
00005b c016 rjmp END
_S3_TIMER:
00005c 98c2 cbi LED_PORT, ROAD_G_LED
00005d e004
00005e 9300 0060 stsi STATE, 4
000060 d022 rcall TIMER_OFF
000061 c010 rjmp END
_S4: ; State 4
000062 3024 cpi t3, 4
000063 f471 brne END
000064 d025 rcall TIMER_ON
000065 3032 cpi timer_secs, 2
000066 f029 breq _S4_TIMER
000067 9ac2 sbi LED_PORT, ROAD_G_LED
000068 d025 rcall DELAY
000069 98c2 cbi LED_PORT, ROAD_G_LED
00006a d023 rcall DELAY
00006b c006 rjmp END
_S4_TIMER:
00006c 98c2 cbi LED_PORT, ROAD_G_LED
00006d e002
00006e 9300 0060 stsi STATE, 2
000070 9468 set
000071 d011 rcall TIMER_OFF
END:
000072 cfa7 rjmp LOOP
MCU_SLEEP:
000073 b705 in t1, MCUCR
000074 6200 ori t1, (1<<SE)
000075 bf05 out MCUCR, t1
000076 2700 clr t1
000077 bb08 out LED_PORT, t1
000078 9588 sleep
TIMER1_COMPA: ; Increment timer seconds register
000079 930f push t1
00007a 931f push t2
00007b b70f in t1, SREG
00007c 9533 inc timer_secs
00007d 2711 clr t2
00007e bd1f out TCNT1, t2
00007f bf0f out SREG, t1
000080 911f pop t2
000081 910f pop t1
000082 9518 reti
TIMER_OFF:
000083 b700 in t1, TCCR1
000084 7f00 andi t1, ~(TIMER1_PRESCALE_MASK)
000085 bf00 out TCCR1, t1
000086 2700 clr t1
000087 bd0f out TCNT1, t1
000088 2f30 mov timer_secs, t1
000089 9508 ret
TIMER_ON:
00008a b700 in t1, TCCR1
00008b 600f ori t1, TIMER1_PRESCALE_MASK
00008c bf00 out TCCR1, t1
00008d 9508 ret
DELAY:
00008e 930f push t1
00008f 931f push t2
000090 ef1f ldi t2, 0xff
_l1:
000091 ef0f ldi t1, 0xff
_l0:
000092 950a dec t1
000093 f7f1 brne _l0
000094 951a dec t2
000095 f7d9 brne _l1
000096 911f pop t2
000097 910f pop t1
RESOURCE USE INFORMATION
------------------------
Notice:
The register and instruction counts are symbol table hit counts,
and hence implicitly used resources are not counted, eg, the
'lpm' instruction without operands implicitly uses r0 and z,
none of which are counted.
x,y,z are separate entities in the symbol table and are
counted separately from r26..r31 here.
.dseg memory usage only counts static data declared with .byte
"ATtiny45" register use summary:
x : 0 y : 0 z : 0 r0 : 0 r1 : 0 r2 : 0 r3 : 0 r4 : 0
r5 : 3 r6 : 0 r7 : 0 r8 : 0 r9 : 0 r10: 0 r11: 0 r12: 0
r13: 0 r14: 0 r15: 0 r16: 55 r17: 8 r18: 6 r19: 7 r20: 0
r21: 0 r22: 0 r23: 0 r24: 0 r25: 0 r26: 0 r27: 0 r28: 0
r29: 0 r30: 0 r31: 0
Registers used: 5 out of 35 (14.3%)
"ATtiny45" instruction use summary:
.lds : 0 .sts : 0 adc : 0 add : 0 adiw : 0 and : 0
andi : 1 asr : 0 bclr : 0 bld : 0 brbc : 0 brbs : 0
brcc : 0 brcs : 0 break : 0 breq : 5 brge : 1 brhc : 0
brhs : 0 brid : 0 brie : 0 brlo : 0 brlt : 0 brmi : 0
brne : 7 brpl : 0 brsh : 0 brtc : 0 brts : 1 brvc : 0
brvs : 0 bset : 0 bst : 0 cbi : 9 cbr : 0 clc : 0
clh : 0 cli : 0 cln : 0 clr : 6 cls : 0 clt : 1
clv : 0 clz : 0 com : 0 cp : 0 cpc : 0 cpi : 11
cpse : 0 dec : 2 eor : 0 icall : 0 ijmp : 0 in : 5
inc : 2 ld : 0 ldd : 0 ldi : 14 lds : 1 lpm : 0
lsl : 0 lsr : 0 mov : 2 movw : 0 neg : 0 nop : 0
or : 0 ori : 3 out : 15 pop : 4 push : 4 rcall : 14
ret : 3 reti : 1 rjmp : 14 rol : 0 ror : 0 sbc : 0
sbci : 0 sbi : 7 sbic : 0 sbis : 0 sbiw : 0 sbr : 0
sbrc : 0 sbrs : 0 sec : 0 seh : 0 sei : 1 sen : 0
ser : 0 ses : 0 set : 1 sev : 0 sez : 0 sleep : 1
spm : 0 st : 0 std : 0 sts : 7 sub : 0 subi : 0
swap : 0 tst : 0 wdr : 0
Instructions used: 28 out of 105 (26.7%)
"ATtiny45" memory use summary [bytes]:
Segment Begin End Code Data Used Size Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x000132 302 0 302 4096 7.4%
[.dseg] 0x000060 0x000061 0 1 1 256 0.4%
[.eseg] 0x000000 0x000000 0 0 0 256 0.0%
Assembly complete, 0 errors, 0 warnings

479
dist/default/production/attiny45v_traffic-lights.X.production.map vendored Normal file
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@ -0,0 +1,479 @@
AVRASM ver. 2.2.7 firmware.asm Fri Oct 06 19:23:41 2023
EQU SIGNATURE_000 0000001e
EQU SIGNATURE_001 00000092
EQU SIGNATURE_002 00000006
EQU SREG 0000003f
EQU SPL 0000003d
EQU SPH 0000003e
EQU GIMSK 0000003b
EQU GIFR 0000003a
EQU TIMSK 00000039
EQU TIFR 00000038
EQU SPMCSR 00000037
EQU MCUCR 00000035
EQU MCUSR 00000034
EQU TCCR0B 00000033
EQU TCNT0 00000032
EQU OSCCAL 00000031
EQU TCCR1 00000030
EQU TCNT1 0000002f
EQU OCR1A 0000002e
EQU OCR1C 0000002d
EQU GTCCR 0000002c
EQU OCR1B 0000002b
EQU TCCR0A 0000002a
EQU OCR0A 00000029
EQU OCR0B 00000028
EQU PLLCSR 00000027
EQU CLKPR 00000026
EQU DT1A 00000025
EQU DT1B 00000024
EQU DTPS 00000023
EQU DWDR 00000022
EQU WDTCR 00000021
EQU PRR 00000020
EQU EEARH 0000001f
EQU EEARL 0000001e
EQU EEDR 0000001d
EQU EECR 0000001c
EQU PORTB 00000018
EQU DDRB 00000017
EQU PINB 00000016
EQU PCMSK 00000015
EQU DIDR0 00000014
EQU GPIOR2 00000013
EQU GPIOR1 00000012
EQU GPIOR0 00000011
EQU USIBR 00000010
EQU USIDR 0000000f
EQU USISR 0000000e
EQU USICR 0000000d
EQU ACSR 00000008
EQU ADMUX 00000007
EQU ADCSRA 00000006
EQU ADCH 00000005
EQU ADCL 00000004
EQU ADCSRB 00000003
EQU PORTB0 00000000
EQU PB0 00000000
EQU PORTB1 00000001
EQU PB1 00000001
EQU PORTB2 00000002
EQU PB2 00000002
EQU PORTB3 00000003
EQU PB3 00000003
EQU PORTB4 00000004
EQU PB4 00000004
EQU PORTB5 00000005
EQU PB5 00000005
EQU DDB0 00000000
EQU DDB1 00000001
EQU DDB2 00000002
EQU DDB3 00000003
EQU DDB4 00000004
EQU DDB5 00000005
EQU PINB0 00000000
EQU PINB1 00000001
EQU PINB2 00000002
EQU PINB3 00000003
EQU PINB4 00000004
EQU PINB5 00000005
EQU ACME 00000006
EQU ACIS0 00000000
EQU ACIS1 00000001
EQU ACIE 00000003
EQU ACI 00000004
EQU ACO 00000005
EQU ACBG 00000006
EQU AINBG 00000006
EQU ACD 00000007
EQU AIN0D 00000000
EQU AIN1D 00000001
EQU MUX0 00000000
EQU MUX1 00000001
EQU MUX2 00000002
EQU MUX3 00000003
EQU REFS2 00000004
EQU ADLAR 00000005
EQU REFS0 00000006
EQU REFS1 00000007
EQU ADPS0 00000000
EQU ADPS1 00000001
EQU ADPS2 00000002
EQU ADIE 00000003
EQU ADIF 00000004
EQU ADATE 00000005
EQU ADSC 00000006
EQU ADEN 00000007
EQU ADCH0 00000000
EQU ADCH1 00000001
EQU ADCH2 00000002
EQU ADCH3 00000003
EQU ADCH4 00000004
EQU ADCH5 00000005
EQU ADCH6 00000006
EQU ADCH7 00000007
EQU ADCL0 00000000
EQU ADCL1 00000001
EQU ADCL2 00000002
EQU ADCL3 00000003
EQU ADCL4 00000004
EQU ADCL5 00000005
EQU ADCL6 00000006
EQU ADCL7 00000007
EQU ADTS0 00000000
EQU ADTS1 00000001
EQU ADTS2 00000002
EQU IPR 00000005
EQU BIN 00000007
EQU ADC1D 00000002
EQU ADC3D 00000003
EQU ADC2D 00000004
EQU ADC0D 00000005
EQU USIBR0 00000000
EQU USIBR1 00000001
EQU USIBR2 00000002
EQU USIBR3 00000003
EQU USIBR4 00000004
EQU USIBR5 00000005
EQU USIBR6 00000006
EQU USIBR7 00000007
EQU USIDR0 00000000
EQU USIDR1 00000001
EQU USIDR2 00000002
EQU USIDR3 00000003
EQU USIDR4 00000004
EQU USIDR5 00000005
EQU USIDR6 00000006
EQU USIDR7 00000007
EQU USICNT0 00000000
EQU USICNT1 00000001
EQU USICNT2 00000002
EQU USICNT3 00000003
EQU USIDC 00000004
EQU USIPF 00000005
EQU USIOIF 00000006
EQU USISIF 00000007
EQU USITC 00000000
EQU USICLK 00000001
EQU USICS0 00000002
EQU USICS1 00000003
EQU USIWM0 00000004
EQU USIWM1 00000005
EQU USIOIE 00000006
EQU USISIE 00000007
EQU ISC00 00000000
EQU ISC01 00000001
EQU GICR 0000003b
EQU PCIE 00000005
EQU INT0 00000006
EQU PCIF 00000005
EQU INTF0 00000006
EQU PCINT0 00000000
EQU PCINT1 00000001
EQU PCINT2 00000002
EQU PCINT3 00000003
EQU PCINT4 00000004
EQU PCINT5 00000005
EQU EEAR0 00000000
EQU EEAR1 00000001
EQU EEAR2 00000002
EQU EEAR3 00000003
EQU EEAR4 00000004
EQU EEAR5 00000005
EQU EEAR6 00000006
EQU EEAR7 00000007
EQU EEAR8 00000000
EQU EEDR0 00000000
EQU EEDR1 00000001
EQU EEDR2 00000002
EQU EEDR3 00000003
EQU EEDR4 00000004
EQU EEDR5 00000005
EQU EEDR6 00000006
EQU EEDR7 00000007
EQU EERE 00000000
EQU EEPE 00000001
EQU EEMPE 00000002
EQU EERIE 00000003
EQU EEPM0 00000004
EQU EEPM1 00000005
EQU WDTCSR 00000021
EQU WDP0 00000000
EQU WDP1 00000001
EQU WDP2 00000002
EQU WDE 00000003
EQU WDCE 00000004
EQU WDTOE 00000004
EQU WDP3 00000005
EQU WDIE 00000006
EQU WDIF 00000007
EQU TOIE0 00000001
EQU OCIE0B 00000003
EQU OCIE0A 00000004
EQU TOV0 00000001
EQU OCF0B 00000003
EQU OCF0A 00000004
EQU WGM00 00000000
EQU WGM01 00000001
EQU COM0B0 00000004
EQU COM0B1 00000005
EQU COM0A0 00000006
EQU COM0A1 00000007
EQU CS00 00000000
EQU CS01 00000001
EQU CS02 00000002
EQU WGM02 00000003
EQU FOC0B 00000006
EQU FOC0A 00000007
EQU TCNT0_0 00000000
EQU TCNT0_1 00000001
EQU TCNT0_2 00000002
EQU TCNT0_3 00000003
EQU TCNT0_4 00000004
EQU TCNT0_5 00000005
EQU TCNT0_6 00000006
EQU TCNT0_7 00000007
EQU OCR0_0 00000000
EQU OCR0_1 00000001
EQU OCR0_2 00000002
EQU OCR0_3 00000003
EQU OCR0_4 00000004
EQU OCR0_5 00000005
EQU OCR0_6 00000006
EQU OCR0_7 00000007
EQU PSR0 00000000
EQU TSM 00000007
EQU CS10 00000000
EQU CS11 00000001
EQU CS12 00000002
EQU CS13 00000003
EQU COM1A0 00000004
EQU COM1A1 00000005
EQU PWM1A 00000006
EQU CTC1 00000007
EQU TCNT1_0 00000000
EQU TCNT1_1 00000001
EQU TCNT1_2 00000002
EQU TCNT1_3 00000003
EQU TCNT1_4 00000004
EQU TCNT1_5 00000005
EQU TCNT1_6 00000006
EQU TCNT1_7 00000007
EQU OCR1A0 00000000
EQU OCR1A1 00000001
EQU OCR1A2 00000002
EQU OCR1A3 00000003
EQU OCR1A4 00000004
EQU OCR1A5 00000005
EQU OCR1A6 00000006
EQU OCR1A7 00000007
EQU OCR1B0 00000000
EQU OCR1B1 00000001
EQU OCR1B2 00000002
EQU OCR1B3 00000003
EQU OCR1B4 00000004
EQU OCR1B5 00000005
EQU OCR1B6 00000006
EQU OCR1B7 00000007
EQU OCR1C0 00000000
EQU OCR1C1 00000001
EQU OCR1C2 00000002
EQU OCR1C3 00000003
EQU OCR1C4 00000004
EQU OCR1C5 00000005
EQU OCR1C6 00000006
EQU OCR1C7 00000007
EQU TOIE1 00000002
EQU OCIE1B 00000005
EQU OCIE1A 00000006
EQU TOV1 00000002
EQU OCF1B 00000005
EQU OCF1A 00000006
EQU PSR1 00000001
EQU FOC1A 00000002
EQU FOC1B 00000003
EQU COM1B0 00000004
EQU COM1B1 00000005
EQU PWM1B 00000006
EQU DTPS0 00000000
EQU DTPS1 00000001
EQU DTVL0 00000000
EQU DTVL1 00000001
EQU DTVL2 00000002
EQU DTVL3 00000003
EQU DTVH0 00000004
EQU DTVH1 00000005
EQU DTVH2 00000006
EQU DTVH3 00000007
EQU SREG_C 00000000
EQU SREG_Z 00000001
EQU SREG_N 00000002
EQU SREG_V 00000003
EQU SREG_S 00000004
EQU SREG_H 00000005
EQU SREG_T 00000006
EQU SREG_I 00000007
EQU BODSE 00000002
EQU SM0 00000003
EQU SM1 00000004
EQU SE 00000005
EQU PUD 00000006
EQU BODS 00000007
EQU PORF 00000000
EQU EXTRF 00000001
EQU BORF 00000002
EQU WDRF 00000003
EQU PRADC 00000000
EQU PRUSI 00000001
EQU PRTIM0 00000002
EQU PRTIM1 00000003
EQU CAL0 00000000
EQU CAL1 00000001
EQU CAL2 00000002
EQU CAL3 00000003
EQU CAL4 00000004
EQU CAL5 00000005
EQU CAL6 00000006
EQU CAL7 00000007
EQU PLOCK 00000000
EQU PLLE 00000001
EQU PCKE 00000002
EQU LSM 00000007
EQU CLKPS0 00000000
EQU CLKPS1 00000001
EQU CLKPS2 00000002
EQU CLKPS3 00000003
EQU CLKPCE 00000007
EQU DWDR0 00000000
EQU DWDR1 00000001
EQU DWDR2 00000002
EQU DWDR3 00000003
EQU DWDR4 00000004
EQU DWDR5 00000005
EQU DWDR6 00000006
EQU DWDR7 00000007
EQU GPIOR20 00000000
EQU GPIOR21 00000001
EQU GPIOR22 00000002
EQU GPIOR23 00000003
EQU GPIOR24 00000004
EQU GPIOR25 00000005
EQU GPIOR26 00000006
EQU GPIOR27 00000007
EQU GPIOR10 00000000
EQU GPIOR11 00000001
EQU GPIOR12 00000002
EQU GPIOR13 00000003
EQU GPIOR14 00000004
EQU GPIOR15 00000005
EQU GPIOR16 00000006
EQU GPIOR17 00000007
EQU GPIOR00 00000000
EQU GPIOR01 00000001
EQU GPIOR02 00000002
EQU GPIOR03 00000003
EQU GPIOR04 00000004
EQU GPIOR05 00000005
EQU GPIOR06 00000006
EQU GPIOR07 00000007
EQU SPMEN 00000000
EQU PGERS 00000001
EQU PGWRT 00000002
EQU RFLB 00000003
EQU CTPB 00000004
EQU LB1 00000000
EQU LB2 00000001
EQU CKSEL0 00000000
EQU CKSEL1 00000001
EQU CKSEL2 00000002
EQU CKSEL3 00000003
EQU SUT0 00000004
EQU SUT1 00000005
EQU CKOUT 00000006
EQU CKDIV8 00000007
EQU BODLEVEL0 00000000
EQU BODLEVEL1 00000001
EQU BODLEVEL2 00000002
EQU EESAVE 00000003
EQU WDTON 00000004
EQU SPIEN 00000005
EQU DWEN 00000006
EQU RSTDISBL 00000007
EQU SELFPRGEN 00000000
DEF XH r27
DEF XL r26
DEF YH r29
DEF YL r28
DEF ZH r31
DEF ZL r30
EQU FLASHEND 000007ff
EQU IOEND 0000003f
EQU SRAM_START 00000060
EQU SRAM_SIZE 00000100
EQU RAMEND 0000015f
EQU XRAMEND 00000000
EQU E2END 000000ff
EQU EEPROMEND 000000ff
EQU EEADRBITS 00000008
EQU NRWW_START_ADDR 00000000
EQU NRWW_STOP_ADDR 000007ff
EQU RWW_START_ADDR 00000000
EQU RWW_STOP_ADDR 00000000
EQU PAGESIZE 00000020
EQU INT0addr 00000001
EQU PCI0addr 00000002
EQU OC1Aaddr 00000003
EQU OVF1addr 00000004
EQU OVF0addr 00000005
EQU ERDYaddr 00000006
EQU ACIaddr 00000007
EQU ADCCaddr 00000008
EQU OC1Baddr 00000009
EQU OC0Aaddr 0000000a
EQU OC0Baddr 0000000b
EQU WDTaddr 0000000c
EQU USI_STARTaddr 0000000d
EQU USI_OVFaddr 0000000e
EQU INT_VECTORS_SIZE 0000000f
DEF cycles r5
DEF t1 r16
DEF t2 r17
DEF t3 r18
DEF timer_secs r19
EQU ROAD_R_LED 00000000
EQU ROAD_Y_LED 00000001
EQU ROAD_G_LED 00000002
EQU WALK_R_LED 00000003
EQU WALK_G_LED 00000004
EQU LED_DIR 00000017
EQU LED_PORT 00000018
EQU MAX_CYCLES 00000002
EQU TIMER1_PRESCALE_MASK 0000000f
DSEG STATE 00000060
CSEG RESET_vect 00000004
CSEG TIMER1_COMPA 00000079
CSEG INIT 00000006
CSEG LOOP 0000001a
CSEG _S0 0000001c
CSEG _S1 0000002b
CSEG TIMER_ON 0000008a
CSEG _S0_TIMER 00000024
CSEG END 00000072
CSEG TIMER_OFF 00000083
CSEG _S2 0000003e
CSEG _S1_TIMER 00000035
CSEG DELAY 0000008e
CSEG MCU_SLEEP 00000073
CSEG _S3 00000055
CSEG _S2_TIMER 00000045
CSEG _CYCLE_DONE 00000048
CSEG _S2_NEXT 0000004e
CSEG _S4 00000062
CSEG _S3_TIMER 0000005c
CSEG _S4_TIMER 0000006c
CSEG _l1 00000091
CSEG _l0 00000092

BIN
dist/default/production/attiny45v_traffic-lights.X.production.obj vendored Normal file
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Binary file not shown.

50
dist/default/production/attiny45v_traffic-lights.X.production.tmp vendored Normal file
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<ASSEMBLER_INFO>
<VERSION>2.2.7</VERSION>
<DEVICE>"ATtiny45"</DEVICE>
<WORKING_DIR>Z:\home\sergeyyarkov\Documents\Projects\Firmwares\AVR\attiny45v_traffic-lights.X</WORKING_DIR>
<INCLUDE_PATH>
<DIR>/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc</DIR>
<DIR></DIR>
</INCLUDE_PATH>
<SOURCE_FILE>firmware.asm</SOURCE_FILE>
<INCLUDED_FILES>
<FILE>/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151/avrasm/inc\tn45def.inc</FILE>
<FILE>definitions.asm</FILE>
</INCLUDED_FILES>
<OBJECT_FILES>
<FILE>dist/default/production/attiny45v_traffic-lights.X.production.obj</FILE>
</OBJECT_FILES>
<HEX_FILES>
<FILE>dist/default/production/attiny45v_traffic-lights.X.production.hex</FILE>
</HEX_FILES>
<OUTPUT_FILES>
<FILE>dist/default/production/attiny45v_traffic-lights.X.production.map</FILE>
<FILE>dist/default/production/attiny45v_traffic-lights.X.production.lss</FILE>
</OUTPUT_FILES>
<LABELS>
<STATE><FILE>firmware.asm</FILE><LINE>29</LINE></STATE>
<RESET_vect><FILE>firmware.asm</FILE><LINE>39</LINE></RESET_vect>
<TIMER1_COMPA><FILE>firmware.asm</FILE><LINE>174</LINE></TIMER1_COMPA>
<INIT><FILE>firmware.asm</FILE><LINE>43</LINE></INIT>
<LOOP><FILE>firmware.asm</FILE><LINE>69</LINE></LOOP>
<_S0><FILE>firmware.asm</FILE><LINE>71</LINE></_S0>
<_S1><FILE>firmware.asm</FILE><LINE>88</LINE></_S1>
<TIMER_ON><FILE>firmware.asm</FILE><LINE>195</LINE></TIMER_ON>
<_S0_TIMER><FILE>firmware.asm</FILE><LINE>80</LINE></_S0_TIMER>
<END><FILE>firmware.asm</FILE><LINE>163</LINE></END>
<TIMER_OFF><FILE>firmware.asm</FILE><LINE>186</LINE></TIMER_OFF>
<_S2><FILE>firmware.asm</FILE><LINE>109</LINE></_S2>
<_S1_TIMER><FILE>firmware.asm</FILE><LINE>99</LINE></_S1_TIMER>
<DELAY><FILE>firmware.asm</FILE><LINE>201</LINE></DELAY>
<MCU_SLEEP><FILE>firmware.asm</FILE><LINE>166</LINE></MCU_SLEEP>
<_S3><FILE>firmware.asm</FILE><LINE>133</LINE></_S3>
<_S2_TIMER><FILE>firmware.asm</FILE><LINE>117</LINE></_S2_TIMER>
<_CYCLE_DONE><FILE>firmware.asm</FILE><LINE>121</LINE></_CYCLE_DONE>
<_S2_NEXT><FILE>firmware.asm</FILE><LINE>126</LINE></_S2_NEXT>
<_S4><FILE>firmware.asm</FILE><LINE>147</LINE></_S4>
<_S3_TIMER><FILE>firmware.asm</FILE><LINE>141</LINE></_S3_TIMER>
<_S4_TIMER><FILE>firmware.asm</FILE><LINE>158</LINE></_S4_TIMER>
<_l1><FILE>firmware.asm</FILE><LINE>205</LINE></_l1>
<_l0><FILE>firmware.asm</FILE><LINE>207</LINE></_l0>
</LABELS>
</ASSEMBLER_INFO>

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#
# Generated Makefile - do not edit!
#
# Edit the Makefile in the project folder instead (../Makefile). Each target
# has a -pre and a -post target defined where you can add customized code.
#
# This makefile implements configuration specific macros and targets.
# Include project Makefile
ifeq "${IGNORE_LOCAL}" "TRUE"
# do not include local makefile. User is passing all local related variables already
else
include Makefile
# Include makefile containing local settings
ifeq "$(wildcard nbproject/Makefile-local-default.mk)" "nbproject/Makefile-local-default.mk"
include nbproject/Makefile-local-default.mk
endif
endif
# Environment
MKDIR=mkdir -p
RM=rm -f
MV=mv
CP=cp
# Macros
CND_CONF=default
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
IMAGE_TYPE=debug
OUTPUT_SUFFIX=obj
DEBUGGABLE_SUFFIX=obj
FINAL_IMAGE=${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
else
IMAGE_TYPE=production
OUTPUT_SUFFIX=obj
DEBUGGABLE_SUFFIX=obj
FINAL_IMAGE=${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
endif
ifeq ($(COMPARE_BUILD), true)
COMPARISON_BUILD=
else
COMPARISON_BUILD=
endif
ifdef SUB_IMAGE_ADDRESS
else
SUB_IMAGE_ADDRESS_COMMAND=
endif
# Object Directory
OBJECTDIR=build/${CND_CONF}/${IMAGE_TYPE}
# Distribution Directory
DISTDIR=dist/${CND_CONF}/${IMAGE_TYPE}
# Source Files Quoted if spaced
SOURCEFILES_QUOTED_IF_SPACED=firmware.asm
# Object Files Quoted if spaced
OBJECTFILES_QUOTED_IF_SPACED=${OBJECTDIR}/firmware.obj
POSSIBLE_DEPFILES=${OBJECTDIR}/firmware.obj.d
# Object Files
OBJECTFILES=${OBJECTDIR}/firmware.obj
# Source Files
SOURCEFILES=firmware.asm
# Pack Options
PACK_ASSEMBLER_OPTIONS=-I "${DFP_DIR}/avrasm/inc" -i tn45def.inc
CFLAGS=
ASFLAGS=
LDLIBSOPTIONS=
############# Tool locations ##########################################
# If you copy a project from one host to another, the path where the #
# compiler is installed may be different. #
# If you open this project with MPLAB X in the new host, this #
# makefile will be regenerated and the paths will be corrected. #
#######################################################################
# fixDeps replaces a bunch of sed/cat/printf statements that slow down the build
FIXDEPS=fixDeps
.build-conf: ${BUILD_SUBPROJECTS}
ifneq ($(INFORMATION_MESSAGE), )
@echo $(INFORMATION_MESSAGE)
endif
${MAKE} -f nbproject/Makefile-default.mk ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}
# ------------------------------------------------------------------------------------
# Rules for buildStep: assemble
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
${OBJECTDIR}/firmware.obj: firmware.asm nbproject/Makefile-${CND_CONF}.mk
@${MKDIR} ${DISTDIR}
@${MKDIR} "${OBJECTDIR}"
@${RM} ${OBJECTDIR}/firmware.obj
${MP_AS} -fI -W+ie ${PACK_ASSEMBLER_OPTIONS} -d ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} -m ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.map -S ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.tmp firmware.asm
else
${OBJECTDIR}/firmware.obj: firmware.asm nbproject/Makefile-${CND_CONF}.mk
@${MKDIR} ${DISTDIR}
@${MKDIR} "${OBJECTDIR}"
@${RM} ${OBJECTDIR}/firmware.obj
${MP_AS} -fI -W+ie ${PACK_ASSEMBLER_OPTIONS} -d ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${DEBUGGABLE_SUFFIX} -S ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.tmp -o ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.hex -m ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.map -l ${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.lss firmware.asm
endif
# ------------------------------------------------------------------------------------
# Rules for buildStep: link
ifeq ($(TYPE_IMAGE), DEBUG_RUN)
${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk
else
${DISTDIR}/attiny45v_traffic-lights.X.${IMAGE_TYPE}.${OUTPUT_SUFFIX}: ${OBJECTFILES} nbproject/Makefile-${CND_CONF}.mk
endif
# Subprojects
.build-subprojects:
# Subprojects
.clean-subprojects:
# Clean Targets
.clean-conf: ${CLEAN_SUBPROJECTS}
${RM} -r ${OBJECTDIR}
${RM} -r ${DISTDIR}
# Enable dependency checking
.dep.inc: .depcheck-impl
DEPFILES=$(shell "${PATH_TO_IDE_BIN}"mplabwildcard ${POSSIBLE_DEPFILES})
ifneq (${DEPFILES},)
include ${DEPFILES}
endif

14
nbproject/Makefile-genesis.properties Normal file
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@ -0,0 +1,14 @@
#
#Fri Oct 06 19:22:35 MSK 2023
default.languagetoolchain.version=2.2.7
default.Pack.dfplocation=/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151
conf.ids=default
default.languagetoolchain.dir=/usr/bin
host.id=2l3s-yrgx-1d
configurations-xml=091e9e6e597d380abcff25658472fdae
default.com-microchip-mplab-nbide-toolchain-avrasm-AVRASMLanguageToolchain.md5=0e94da8ed93e9650ffef50929833a79f
default.com-microchip-mplab-mdbcore-snap-SnapToolImpl.md5=eaa336cefb7fc46db8b50b7b2b6e54ca
com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=6e02ca5e9f5042ffd365b42ab82d3a9b
user-defined-mime-resolver-xml=none
proj.dir=/home/sergeyyarkov/Documents/Projects/Firmwares/AVR/attiny45v_traffic-lights.X
host.platform=linux

69
nbproject/Makefile-impl.mk Normal file
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#
# Generated Makefile - do not edit!
#
# Edit the Makefile in the project folder instead (../Makefile). Each target
# has a pre- and a post- target defined where you can add customization code.
#
# This makefile implements macros and targets common to all configurations.
#
# NOCDDL
# Building and Cleaning subprojects are done by default, but can be controlled with the SUB
# macro. If SUB=no, subprojects will not be built or cleaned. The following macro
# statements set BUILD_SUB-CONF and CLEAN_SUB-CONF to .build-reqprojects-conf
# and .clean-reqprojects-conf unless SUB has the value 'no'
SUB_no=NO
SUBPROJECTS=${SUB_${SUB}}
BUILD_SUBPROJECTS_=.build-subprojects
BUILD_SUBPROJECTS_NO=
BUILD_SUBPROJECTS=${BUILD_SUBPROJECTS_${SUBPROJECTS}}
CLEAN_SUBPROJECTS_=.clean-subprojects
CLEAN_SUBPROJECTS_NO=
CLEAN_SUBPROJECTS=${CLEAN_SUBPROJECTS_${SUBPROJECTS}}
# Project Name
PROJECTNAME=attiny45v_traffic-lights.X
# Active Configuration
DEFAULTCONF=default
CONF=${DEFAULTCONF}
# All Configurations
ALLCONFS=default
# build
.build-impl: .build-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .build-conf
# clean
.clean-impl: .clean-pre
${MAKE} -f nbproject/Makefile-${CONF}.mk SUBPROJECTS=${SUBPROJECTS} .clean-conf
# clobber
.clobber-impl: .clobber-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default clean
# all
.all-impl: .all-pre .depcheck-impl
${MAKE} SUBPROJECTS=${SUBPROJECTS} CONF=default build
# dependency checking support
.depcheck-impl:
# @echo "# This code depends on make tool being used" >.dep.inc
# @if [ -n "${MAKE_VERSION}" ]; then \
# echo "DEPFILES=\$$(wildcard \$$(addsuffix .d, \$${OBJECTFILES}))" >>.dep.inc; \
# echo "ifneq (\$${DEPFILES},)" >>.dep.inc; \
# echo "include \$${DEPFILES}" >>.dep.inc; \
# echo "endif" >>.dep.inc; \
# else \
# echo ".KEEP_STATE:" >>.dep.inc; \
# echo ".KEEP_STATE_FILE:.make.state.\$${CONF}" >>.dep.inc; \
# fi

37
nbproject/Makefile-local-default.mk Normal file
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@ -0,0 +1,37 @@
#
# Generated Makefile - do not edit!
#
#
# This file contains information about the location of compilers and other tools.
# If you commmit this file into your revision control server, you will be able to
# to checkout the project and build it from the command line with make. However,
# if more than one person works on the same project, then this file might show
# conflicts since different users are bound to have compilers in different places.
# In that case you might choose to not commit this file and let MPLAB X recreate this file
# for each user. The disadvantage of not commiting this file is that you must run MPLAB X at
# least once so the file gets created and the project can be built. Finally, you can also
# avoid using this file at all if you are only building from the command line with make.
# You can invoke make with the values of the macros:
# $ makeMP_CC="/opt/microchip/mplabc30/v3.30c/bin/pic30-gcc" ...
#
PATH_TO_IDE_BIN=/opt/microchip/mplabx/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/
# Adding MPLAB X bin directory to path.
PATH:=/opt/microchip/mplabx/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/:$(PATH)
# Path to java used to run MPLAB X when this makefile was created
MP_JAVA_PATH="/opt/microchip/mplabx/v6.00/sys/java/zulu8.54.0.21-ca-fx-jre8.0.292-linux_x64/bin/"
OS_CURRENT="$(shell uname -s)"
# MP_CC is not defined
# MP_CPPC is not defined
# MP_BC is not defined
MP_AS="/usr/bin/avrasm2"
# MP_LD is not defined
# MP_AR is not defined
DEP_GEN=${MP_JAVA_PATH}java -jar "/opt/microchip/mplabx/v6.00/mplab_platform/platform/../mplab_ide/modules/../../bin/extractobjectdependencies.jar"
# MP_CC_DIR is not defined
# MP_CPPC_DIR is not defined
# MP_BC_DIR is not defined
MP_AS_DIR="/usr/bin"
# MP_LD_DIR is not defined
# MP_AR_DIR is not defined
# MP_BC_DIR is not defined
DFP_DIR=/home/sergeyyarkov/.mchp_packs/Microchip/ATtiny_DFP/3.0.151

10
nbproject/Makefile-variables.mk Normal file
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@ -0,0 +1,10 @@
#
# Generated - do not edit!
#
# NOCDDL
#
CND_BASEDIR=`pwd`
# default configuration
CND_ARTIFACT_DIR_default=dist/default/production
CND_ARTIFACT_NAME_default=attiny45v_traffic-lights.X.production.obj
CND_ARTIFACT_PATH_default=dist/default/production/attiny45v_traffic-lights.X.production.obj

176
nbproject/configurations.xml Normal file
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@ -0,0 +1,176 @@
<?xml version="1.0" encoding="UTF-8"?>
<configurationDescriptor version="65">
<logicalFolder name="root" displayName="root" projectFiles="true">
<logicalFolder name="HeaderFiles"
displayName="Header Files"
projectFiles="true">
</logicalFolder>
<logicalFolder name="LinkerScript"
displayName="Linker Files"
projectFiles="true">
</logicalFolder>
<logicalFolder name="SourceFiles"
displayName="Source Files"
projectFiles="true">
<itemPath>firmware.asm</itemPath>
<itemPath>definitions.asm</itemPath>
</logicalFolder>
<logicalFolder name="ExternalFiles"
displayName="Important Files"
projectFiles="false">
<itemPath>Makefile</itemPath>
</logicalFolder>
</logicalFolder>
<projectmakefile>Makefile</projectmakefile>
<confs>
<conf name="default" type="2">
<toolsSet>
<developmentServer>localhost</developmentServer>
<targetDevice>ATtiny45</targetDevice>
<targetHeader></targetHeader>
<targetPluginBoard></targetPluginBoard>
<platformTool>snap</platformTool>
<languageToolchain>AVRASM</languageToolchain>
<languageToolchainVersion>2.2.7</languageToolchainVersion>
<platform>2</platform>
</toolsSet>
<packs>
<pack name="ATtiny_DFP" vendor="Microchip" version="3.0.151"/>
</packs>
<ScriptingSettings>
</ScriptingSettings>
<compileType>
<linkerTool>
<linkerLibItems>
</linkerLibItems>
</linkerTool>
<archiverTool>
</archiverTool>
<loading>
<useAlternateLoadableFile>false</useAlternateLoadableFile>
<parseOnProdLoad>false</parseOnProdLoad>
<alternateLoadableFile></alternateLoadableFile>
</loading>
<subordinates>
</subordinates>
</compileType>
<makeCustomizationType>
<makeCustomizationPreStepEnabled>false</makeCustomizationPreStepEnabled>
<makeUseCleanTarget>false</makeUseCleanTarget>
<makeCustomizationPreStep></makeCustomizationPreStep>
<makeCustomizationPostStepEnabled>false</makeCustomizationPostStepEnabled>
<makeCustomizationPostStep></makeCustomizationPostStep>
<makeCustomizationPutChecksumInUserID>false</makeCustomizationPutChecksumInUserID>
<makeCustomizationEnableLongLines>false</makeCustomizationEnableLongLines>
<makeCustomizationNormalizeHexFile>false</makeCustomizationNormalizeHexFile>
</makeCustomizationType>
<AVR-ASM>
<property key="hex-format" value="I"/>
<property key="unsupported-instructions" value="e"/>
<property key="wrap-relative-jumps" value="false"/>
</AVR-ASM>
<AVR-Global>
<property key="generate-eep-file" value="false"/>
<property key="generate-hex-file" value="true"/>
<property key="generate-lss-file" value="true"/>
<property key="generate-map-file" value="true"/>
</AVR-Global>
<Tool>
<property key="AutoSelectMemRanges" value="auto"/>
<property key="ToolFirmwareFilePath"
value="Press to browse for a specific firmware version"/>
<property key="ToolFirmwareOption.UpdateOptions"
value="ToolFirmwareOption.UseLatest"/>
<property key="ToolFirmwareToolPack"
value="Press to select which tool pack to use"/>
<property key="communication.interface" value="dw"/>
<property key="communication.interface.jtag" value="2wire"/>
<property key="communication.speed" value="0.125"/>
<property key="debugoptions.debug-startup" value="Use system settings"/>
<property key="debugoptions.reset-behaviour" value="Use system settings"/>
<property key="debugoptions.simultaneous.debug" value="false"/>
<property key="debugoptions.useswbreakpoints" value="false"/>
<property key="freeze.timers" value="false"/>
<property key="memories.aux" value="false"/>
<property key="memories.bootflash" value="true"/>
<property key="memories.configurationmemory" value="true"/>
<property key="memories.configurationmemory2" value="true"/>
<property key="memories.dataflash" value="true"/>
<property key="memories.eeprom" value="true"/>
<property key="memories.exclude.configurationmemory" value="true"/>
<property key="memories.flashdata" value="true"/>
<property key="memories.id" value="true"/>
<property key="memories.instruction.ram.ranges"
value="${memories.instruction.ram.ranges}"/>
<property key="memories.programmemory" value="true"/>
<property key="memories.programmemory.ranges" value="0-7ff"/>
<property key="programoptions.donoteraseauxmem" value="false"/>
<property key="programoptions.eraseb4program" value="true"/>
<property key="programoptions.pgmentry.voltage" value="low"/>
<property key="programoptions.pgmspeed" value="Med"/>
<property key="programoptions.preservedataflash" value="false"/>
<property key="programoptions.preservedataflash.ranges" value="0-ff"/>
<property key="programoptions.preserveeeprom" value="false"/>
<property key="programoptions.preserveeeprom.ranges" value=""/>
<property key="programoptions.preserveprogram.ranges" value=""/>
<property key="programoptions.preserveprogramrange" value="false"/>
<property key="programoptions.programcalmem" value="false"/>
<property key="programoptions.programuserotp" value="false"/>
<property key="programoptions.testmodeentrymethod" value="VDDFirst"/>
<property key="toolpack.updateoptions"
value="toolpack.updateoptions.uselatestoolpack"/>
<property key="toolpack.updateoptions.packversion"
value="Press to select which tool pack to use"/>
</Tool>
<item path="definitions.asm" ex="true" overriding="false">
</item>
<snap>
<property key="AutoSelectMemRanges" value="auto"/>
<property key="ToolFirmwareFilePath"
value="Press to browse for a specific firmware version"/>
<property key="ToolFirmwareOption.UpdateOptions"
value="ToolFirmwareOption.UseLatest"/>
<property key="ToolFirmwareToolPack"
value="Press to select which tool pack to use"/>
<property key="communication.interface" value="dw"/>
<property key="communication.interface.jtag" value="2wire"/>
<property key="communication.speed" value="0.125"/>
<property key="debugoptions.debug-startup" value="Use system settings"/>
<property key="debugoptions.reset-behaviour" value="Use system settings"/>
<property key="debugoptions.simultaneous.debug" value="false"/>
<property key="debugoptions.useswbreakpoints" value="false"/>
<property key="freeze.timers" value="false"/>
<property key="memories.aux" value="false"/>
<property key="memories.bootflash" value="true"/>
<property key="memories.configurationmemory" value="true"/>
<property key="memories.configurationmemory2" value="true"/>
<property key="memories.dataflash" value="true"/>
<property key="memories.eeprom" value="true"/>
<property key="memories.exclude.configurationmemory" value="true"/>
<property key="memories.flashdata" value="true"/>
<property key="memories.id" value="true"/>
<property key="memories.instruction.ram.ranges"
value="${memories.instruction.ram.ranges}"/>
<property key="memories.programmemory" value="true"/>
<property key="memories.programmemory.ranges" value="0-7ff"/>
<property key="programoptions.donoteraseauxmem" value="false"/>
<property key="programoptions.eraseb4program" value="true"/>
<property key="programoptions.pgmentry.voltage" value="low"/>
<property key="programoptions.pgmspeed" value="Med"/>
<property key="programoptions.preservedataflash" value="false"/>
<property key="programoptions.preservedataflash.ranges" value="0-ff"/>
<property key="programoptions.preserveeeprom" value="false"/>
<property key="programoptions.preserveeeprom.ranges" value=""/>
<property key="programoptions.preserveprogram.ranges" value=""/>
<property key="programoptions.preserveprogramrange" value="false"/>
<property key="programoptions.programcalmem" value="false"/>
<property key="programoptions.programuserotp" value="false"/>
<property key="programoptions.testmodeentrymethod" value="VDDFirst"/>
<property key="toolpack.updateoptions"
value="toolpack.updateoptions.uselatestoolpack"/>
<property key="toolpack.updateoptions.packversion"
value="Press to select which tool pack to use"/>
</snap>
</conf>
</confs>
</configurationDescriptor>

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nbproject/private/configurations.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<configurationDescriptor version="65">
<projectmakefile>Makefile</projectmakefile>
<defaultConf>0</defaultConf>
<confs>
<conf name="default" type="2">
<platformToolSN>:=MPLABComm-USB-Microchip:=&lt;vid>03EB:=&lt;pid>2180:=&lt;rev>0100:=&lt;man>Microchip Technology Incorporated:=&lt;prod>MPLAB Snap ICD CMSIS-DAP:=&lt;sn>BUR205073320:=&lt;drv>x:=&lt;xpt>h:=end</platformToolSN>
<languageToolchainDir>/usr/bin</languageToolchainDir>
<mdbdebugger version="1">
<placeholder1>place holder 1</placeholder1>
<placeholder2>place holder 2</placeholder2>
</mdbdebugger>
<runprofile version="6">
<args></args>
<rundir></rundir>
<buildfirst>true</buildfirst>
<console-type>0</console-type>
<terminal-type>0</terminal-type>
<remove-instrumentation>0</remove-instrumentation>
<environment>
</environment>
</runprofile>
</conf>
</confs>
</configurationDescriptor>

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nbproject/private/private.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project-private xmlns="http://www.netbeans.org/ns/project-private/1">
<editor-bookmarks xmlns="http://www.netbeans.org/ns/editor-bookmarks/2" lastBookmarkId="0"/>
<open-files xmlns="http://www.netbeans.org/ns/projectui-open-files/2">
<group>
<file>file:/home/sergeyyarkov/Documents/Projects/Firmwares/AVR/attiny45v_traffic-lights.X/firmware.asm</file>
</group>
</open-files>
</project-private>

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nbproject/project.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<project xmlns="http://www.netbeans.org/ns/project/1">
<type>com.microchip.mplab.nbide.embedded.makeproject</type>
<configuration>
<data xmlns="http://www.netbeans.org/ns/make-project/1">
<name>attiny45v_traffic-lights</name>
<creation-uuid>bdaa861e-4a16-4a63-b70d-c14ef63cd53a</creation-uuid>
<make-project-type>0</make-project-type>
<c-extensions/>
<cpp-extensions/>
<header-extensions/>
<asminc-extensions/>
<sourceEncoding>UTF-8</sourceEncoding>
<make-dep-projects/>
<sourceRootList/>
<confList>
<confElem>
<name>default</name>
<type>2</type>
</confElem>
</confList>
<formatting>
<project-formatting-style>false</project-formatting-style>
</formatting>
</data>
</configuration>
</project>