#if !defined(PDSP188x_CONFIG_AVR_H_) # define PDSP188x_CONFIG_AVR_H_ # include # include # define DATA_PORT PORTB # define DATA_DIR DDRB /** * Control using 595 shift register */ # define LATCH _BV(PB4) # define DATA _BV(PB5) # define CLK _BV(PB7) /** * Writes data into display when WR=0. Note CE=0 to enable write cycle. */ # define WR _BV(PB0) /** * Accesses Flash RAM. Address inputs A0–A2 select digit address * while data bit D0 sets (D0=1) or resets (D0=0) Flash bit, A3 and A4 ignored */ # define FL _BV(PB1) /** * Initializes display; clears Character RAM (20H), Flash RAM (00H), control word (00H), and resets * internal counters. UDC Address Register and UDC RAM unaffected. */ # define RST _BV(PB6) # define ADDR_PORT PORTC # define ADDR_DIR DDRC /** * A0–A2 select specific digits * A3 and A4 access parts of memory together with Flash pin */ # define A0 _BV(PC3) # define A1 _BV(PC4) # define A2 _BV(PC5) # define A3 _BV(PC6) # define A4 _BV(PC7) #endif